Patents by Inventor Julian Blake

Julian Blake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9799492
    Abstract: Substrate processing systems, such as ion implantation systems, deposition systems and etch systems, having textured silicon liners are disclosed. The silicon liners are textured using a chemical treatment that produces small features, referred to as micropyramids, which may be less than 20 micrometers in height. Despite the fact that these micropyramids are much smaller than the textured features commonly found in graphite liners, the textured silicon is able to hold deposited coatings and resist flaking. Methods for performing preventative maintenance on these substrate processing systems are also disclosed.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: October 24, 2017
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventor: Julian Blake
  • Patent number: 9692325
    Abstract: In accordance with an embodiment of the invention, there is provided an electrostatic chuck comprising a conductive path covering at least a portion of a workpiece-contacting surface of a gas seal ring of the electrostatic chuck, the conductive path comprising at least a portion of an electrical path to ground; and a main field area of a workpiece-contacting surface of the electrostatic chuck comprising a surface resistivity in the range of from about 108 to about 1012 ohms per square.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: June 27, 2017
    Assignees: Entegris, Inc., Varian Semiconductor Equipment Associates, Inc.
    Inventors: David Suuronen, Lyudmila Stone, Julian Blake, Dale K. Stone, Richard A. Cooke, Steven Donnell, Chandra Venkatraman
  • Publication number: 20160343545
    Abstract: Substrate processing systems, such as ion implantation systems, deposition systems and etch systems, having textured silicon liners are disclosed. The silicon liners are textured using a chemical treatment that produces small features, referred to as micropyramids, which may be less than 20 micrometers in height. Despite the fact that these micropyramids are much smaller than the textured features commonly found in graphite liners, the textured silicon is able to hold deposited coatings and resist flaking. Methods for performing preventative maintenance on these substrate processing systems are also disclosed.
    Type: Application
    Filed: August 3, 2016
    Publication date: November 24, 2016
    Inventor: Julian Blake
  • Patent number: 9437397
    Abstract: Substrate processing systems, such as ion implantation systems, deposition systems and etch systems, having textured silicon liners are disclosed. The silicon liners are textured using a chemical treatment that produces small features, referred to as micropyramids, which may be less than 20 micrometers in height. Despite the fact that these micropyramids are much smaller than the textured features commonly found in graphite liners, the textured silicon is able to hold deposited coatings and resist flaking. Methods for performing preventative maintenance on these substrate processing systems are also disclosed.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: September 6, 2016
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventor: Julian Blake
  • Patent number: 9082804
    Abstract: An electrostatic clamp which more effectively removes built up charge from a substrate prior to removal is disclosed. Currently, the lift pins and the ground pins are the only mechanism used to remove charge from the substrate after implantation. The present discloses describes an electrostatic chuck in which the top dielectric surface has an embedded conductive region, such as a ring shaped conductive region in the sealing ring. Thus, regardless of the orientation of the substrate during release, at least a portion of the substrate will contain the conductive region on the dielectric layer of the workpiece support. This conductive region may be connected to ground through the use of conductive vias in the dielectric layer. In some embodiments, these conductive vias are the fluid conduits used to supply gas to the back side of the substrate.
    Type: Grant
    Filed: February 7, 2011
    Date of Patent: July 14, 2015
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Julian Blake, Dale K. Stone, Lyudmila Stone, David Suuronen, Shigeo Oshiro
  • Patent number: 9025305
    Abstract: In accordance with an embodiment of the invention, there is provided an electrostatic chuck. The electrostatic chuck comprises an electrode, and a surface layer activated by a voltage in the electrode to form an electric charge to electrostatically clamp a substrate to the electrostatic chuck, the surface layer including a charge control layer comprising a surface resistivity of greater than about 1011 ohms per square.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: May 5, 2015
    Assignees: Entegris, Inc., Varian Semiconductor Equipment Associates, Inc.
    Inventors: Richard A. Cooke, Dale K. Stone, Lyudmila Stone, Julian Blake, David Suuronen
  • Publication number: 20150001391
    Abstract: Substrate processing systems, such as ion implantation systems, deposition systems and etch systems, having textured silicon liners are disclosed. The silicon liners are textured using a chemical treatment that produces small features, referred to as micropyramids, which may be less than 20 micrometers in height. Despite the fact that these micropyramids are much smaller than the textured features commonly found in graphite liners, the textured silicon is able to hold deposited coatings and resist flaking. Methods for performing preventative maintenance on these substrate processing systems are also disclosed.
    Type: Application
    Filed: June 27, 2013
    Publication date: January 1, 2015
    Inventor: Julian Blake
  • Patent number: 8814239
    Abstract: Techniques for handling media arrays are disclosed. The techniques may be realized as a system for handling a plurality of substrates. The system may comprise a plurality of row elements for supporting the plurality of substrates, wherein the plurality of row elements may be operable to change configuration of the substrates from open configuration to a high-density configuration, where a distance between adjacent substrates in the open configuration may be greater than a distance between the adjacent substrates in the high-density configuration.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: August 26, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Paul Forderhase, Julian Blake, William Weaver
  • Patent number: 8746666
    Abstract: A media carrier, adapted to hold a plurality of pieces of magnetic media, is disclosed. This media carrier can be placed on the workpiece support, or platen, allowing the magnetic media to be processed. In some embodiments, the media carrier is designed such that only one side of the magnetic media is exposed, requiring a robot or other equipment to invert each piece of media in the carrier to process the second side. In other embodiments, the media carrier is designed such that both sides of the magnetic media are exposed. In this scenario, the media carrier is inverted on the platen to allow processing of the second side.
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: June 10, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Richard Hertel, Julian Blake, Edward Macintosh, Alexander Kontos, Frank Sinclair, Christopher Rowland, Mayur Jagtap, Sankar Ganesh Kolappan
  • Patent number: 8598021
    Abstract: A method of implanting ions into a workpiece without the formation of junctions, which impact the performance of the workpiece, is disclosed. To counteract the effect of dopant being implanted into the edge of the workpiece, components made of material having an opposite conductivity are placed near the workpiece. As ions from the beam strike these components, ions from the material are sputtered. These ions have the opposite conductivity as the implanted ions, and therefore inhibit the formation of junctions.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: December 3, 2013
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Julian Blake, Dale Stone
  • Publication number: 20130209198
    Abstract: Techniques for handling media arrays are disclosed. The techniques may be realized as a system for handling a plurality of substrates. The system may comprise a plurality of row elements for supporting the plurality of substrates, wherein the plurality of row elements may be operable to change configuration of the substrates from open configuration to a high-density configuration, where a distance between adjacent substrates in the open configuration may be greater than a distance between the adjacent substrates in the high-density configuration.
    Type: Application
    Filed: February 15, 2012
    Publication date: August 15, 2013
    Applicant: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Paul Forderhase, Julian Blake, William Weaver
  • Publication number: 20130155569
    Abstract: In accordance with an embodiment of the invention, there is provided an electrostatic chuck comprising a conductive path covering at least a portion of a workpiece-contacting surface of a gas seal ring of the electrostatic chuck, the conductive path comprising at least a portion of an electrical path to ground; and a main field area of a workpiece-contacting surface of the electrostatic chuck comprising a surface resistivity in the range of from about 108 to about 1012 ohms per square.
    Type: Application
    Filed: September 8, 2011
    Publication date: June 20, 2013
    Applicants: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC., ENTEGRIS, INC.
    Inventors: David Suuronen, Lyudmila Stone, Julian Blake, Dale K. Stone, Richard A. Cooke, Steven Donnell, Chandra Venkatraman
  • Patent number: 8461552
    Abstract: A particle isolation system includes a semiconductor process chamber; at least one member within the semiconductor process chamber wherein the member has at least a first position and a second position; and at least one isolation compartment having a plurality of walls, the isolation compartment defined by the plurality of walls, at least one of the plurality of walls of the isolation compartment defining at least one opening wherein the member in the first position permits particles to enter the isolation compartment from the semiconductor process chamber through the opening, and wherein the member in the second position substantially encloses the isolation compartment thereby substantially retaining the particles in the isolation compartment and substantially limiting movement of the particles between the semiconductor process chamber and the isolation compartment through the opening. An ion implant system is also provided.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: June 11, 2013
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Peter Nunan, Gregory Redinbo, Julian Blake, Paul S. Buccos
  • Publication number: 20130084694
    Abstract: A method of implanting ions into a workpiece without the formation of junctions, which impact the performance of the workpiece, is disclosed. To counteract the effect of dopant being implanted into the edge of the workpiece, components made of material having an opposite conductivity are placed near the workpiece. As ions from the beam strike these components, ions from the material are sputtered. These ions have the opposite conductivity as the implanted ions, and therefore inhibit the formation of junctions.
    Type: Application
    Filed: September 29, 2011
    Publication date: April 4, 2013
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Julian Blake, Dale Stone
  • Publication number: 20130070384
    Abstract: In accordance with an embodiment of the invention, there is provided an electrostatic chuck. The electrostatic chuck comprises an electrode, and a surface layer activated by a voltage in the electrode to form an electric charge to electrostatically clamp a substrate to the electrostatic chuck, the surface layer including a charge control layer comprising a surface resistivity of greater than about 1011 ohms per square.
    Type: Application
    Filed: May 24, 2011
    Publication date: March 21, 2013
    Applicants: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC., ENTEGRIS, INC.
    Inventors: Richard A. Cooke, Dale K. Stone, Lyudmila Stone, Julian Blake, David Suuronen
  • Publication number: 20120200980
    Abstract: An electrostatic clamp which more effectively removes built up charge from a substrate prior to removal is disclosed. Currently, the lift pins and the ground pins are the only mechanism used to remove charge from the substrate after implantation. The present discloses describes an electrostatic chuck in which the top dielectric surface has an embedded conductive region, such as a ring shaped conductive region in the sealing ring. Thus, regardless of the orientation of the substrate during release, at least a portion of the substrate will contain the conductive region on the dielectric layer of the workpiece support. This conductive region may be connected to ground through the use of conductive vias in the dielectric layer. In some embodiments, these conductive vias are the fluid conduits used to supply gas to the back side of the substrate.
    Type: Application
    Filed: February 7, 2011
    Publication date: August 9, 2012
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Julian Blake, Dale K. Stone, Lyudmila Stone, David Suuronen, Shigeo Oshiro
  • Publication number: 20110207308
    Abstract: A technique for low-temperature ion implantation is disclosed. In one particular exemplary embodiment, the technique may be realized as an apparatus for low-temperature ion implantation. The apparatus may comprise a pre-chill station located in proximity to an end station in an ion implanter; a cooling mechanism within the pre-chill station configured to cool a wafer from ambient temperature to a predetermined range less than ambient temperature; a loading assembly coupled to the pre-chill station and the end station; and a controller in communication with the loading assembly and the cooling mechanism to coordinate loading a wafer into the pre-chill station, cooling the wafer down to the predetermined temperature range before any ion implantation into the wafer, and loading the cooled wafer into the end station where the cooled wafer undergoes an ion implantation process.
    Type: Application
    Filed: May 2, 2011
    Publication date: August 25, 2011
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Jonathan G. ENGLAND, Steven R. Walther, Richard S. Muka, Julian Blake, Paul J. Murphy, Reuel B. Liebert
  • Patent number: 7993698
    Abstract: Techniques for temperature-controlled ion implantation are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for temperature-controlled ion implantation. The apparatus may comprise at least one thermal sensor adapted to measure a temperature of a wafer during an ion implantation process inside an end station of an ion implanter. The apparatus may also comprise a thermal conditioning unit coupled to the end station. The apparatus may further comprise a controller in communication with the thermal sensor and the thermal conditioning unit, wherein the controller compares the measured temperature to a desired wafer temperature and causes the thermal conditioning unit to adjust the temperature of the wafer based upon the comparison.
    Type: Grant
    Filed: September 23, 2006
    Date of Patent: August 9, 2011
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Julian Blake, Jonathan England, Scott Holden, Steven R. Walther, Reuel Liebert, Richard S. Muka, Ukyo Jeong, Jinning Liu, Kyu-Ha Shim, Sandeep Mehta
  • Patent number: 7935942
    Abstract: A technique for low-temperature ion implantation is disclosed. In one particular exemplary embodiment, the technique may be realized as an apparatus for low-temperature ion implantation. The apparatus may comprise a pre-chill station located in proximity to an end station in an ion implanter. The apparatus may also comprise a cooling mechanism within the pre-chill station. The apparatus may further comprise a loading assembly coupled to the pre-chill station and the end station. The apparatus may additionally comprise a controller in communication with the loading assembly and the cooling mechanism to coordinate loading a wafer into the pre-chill station, cooling the wafer down to a predetermined temperature range, and loading the cooled wafer into the end station where the cooled wafer undergoes an ion implantation process.
    Type: Grant
    Filed: August 15, 2006
    Date of Patent: May 3, 2011
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Jonathan England, Steven R. Walther, Richard S. Muka, Julian Blake, Paul J. Murphy, Reuel B. Liebert
  • Publication number: 20110049359
    Abstract: A particle isolation system includes a semiconductor process chamber; at least one member within the semiconductor process chamber wherein the member has at least a first position and a second position; and at least one isolation compartment having a plurality of walls, the isolation compartment defined by the plurality of walls, at least one of the plurality of walls of the isolation compartment defining at least one opening wherein the member in the first position permits particles to enter the isolation compartment from the semiconductor process chamber through the opening, and wherein the member in the second position substantially encloses the isolation compartment thereby substantially retaining the particles in the isolation compartment and substantially limiting movement of the particles between the semiconductor process chamber and the isolation compartment through the opening. An ion implant system is also provided.
    Type: Application
    Filed: November 10, 2010
    Publication date: March 3, 2011
    Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Peter NUNAN, Gregory Redinbo, Julian Blake, Paul S. Buccos