Abstract: A circuit for providing substantially a constant delay of an electrical signal that compensates for voltage, temperature and process variations includes an inverter. A delay cell has an output that is coupled to the inverter. The delay cell includes a charge transistor coupled to a capacitor. A control circuit has an output that is coupled to a gate of the charge transistor. The output has a voltage that is proportional to a trip voltage of the inverter. The delay cell also has a discharge transistor. The control circuit contains a second output that is coupled to a gate of the discharge transistor. The second output has a voltage that is also proportional to the trip voltage of the inverter.

Abstract: A circuit comprising a memory array and a logic circuit. The memory array may be configured to read or write data in response to (i) one or more enable signals and (ii) a global signal. The logic circuit may be configured to generate the enable signals in response to one or more address signals. De-assertion of the enable signals generally reduces current consumption in the memory array.

Abstract: The present invention provides a circuit and method using a floating PMOS transistor connected in series between the transistors of an input invertor. The floating PMOS transistor may be used to control the amount of current through the transistors. The gate of the floating PMOS transistor may be connected through a reference line to a duplicate of the input inverter stage. The duplicate stage is generally located in a reference block and fed with a stabilized reference voltage. Each couple (formed by the buffers input stage and the duplicate stage) functions as a differential comparator, which checks the input voltage against the reference voltage and rejects the power supply voltage variations which are perceived as a common-mode noise signal. The supply current is fixed by the reference voltage which reduces power consumption at high input voltages and high supply voltages.