Patents by Inventor Julian Carlo Barbadillo

Julian Carlo Barbadillo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240063107
    Abstract: An electronic device includes a multilevel package substrate, a semiconductor die mounted to the multilevel package substrate, and a package structure that encloses the semiconductor die and a portion of the multilevel package substrate. The multilevel package substrate has a first level, a second level, a first metal stack, and a second metal stack. The first metal stack includes a first set of contiguous metal structures of the first and second levels, the second metal stack includes a second set of contiguous metal structures of the first and second levels, the first and second metal stacks are spaced apart from one another, a first metal trace of the first metal stack partially overlaps a second metal trace of the second metal stack, and the first and second metal traces are in different levels of the multilevel package substrate.
    Type: Application
    Filed: August 22, 2022
    Publication date: February 22, 2024
    Inventors: Jason Colte, Jerry Cayabyab, Julian Carlo Barbadillo, John Carlo Molina, Richard Sumalinog, Raust Glenn Magcaling, Ruby Ann Camenforte
  • Publication number: 20230378146
    Abstract: An example microelectronic device package includes: a multilayer package substrate comprising routing conductors spaced by dielectric material, the multilayer package substrate having a device side surface and an opposing board side surface, and having a recessed portion extending from the device side surface and exposing routing conductors beneath the device side surface of the multilayer package substrate; a semiconductor die mounted to the device side surface of the multilayer package substrate and coupled to the routing conductors; a passive component mounted to the routing conductors exposed in the recessed portion of the multilayer package substrate; and mold compound covering the semiconductor die, the passive component, and a portion of the multilayer package substrate.
    Type: Application
    Filed: May 18, 2023
    Publication date: November 23, 2023
    Inventors: John Carlo Molina, Julian Carlo Barbadillo, Chun Ping Lo, Sylvester Ankamah-Kusi, Rajen Murugan, Thomas Kronenberg, Jonathan Noquil, Guangxu Li, Blake Travis, Jason Colte
  • Publication number: 20200203227
    Abstract: A method for dicing a wafer includes scribing perforations in a wafer. The wafer has a monocrystalline structure and the perforations have a polycrystalline structures The method also includes adhering the wafer to a top surface of a dicing tape and applying a downward force on a periphery of the dicing tape. The downward force causes a bottom surface of the dicing tape to deform around a contour of a dome shaped chuck, breaking the perforations in the wafer.
    Type: Application
    Filed: March 4, 2020
    Publication date: June 25, 2020
    Inventors: Jerry Gomez Cayabyab, Jennifer Otero Aspuria, Julian Carlo Barbadillo, Alvin Lopez Andaya