Abstract: System and method for creating a graphical program. A first replication structure may be included in a graphical program, where the first replication structure specifies replication of any graphical program code inside the first replication structure. First graphical program code may be included inside the first replication structure. An implementation of the graphical program may be automatically generated, including generating multiple instances of an implementation of the first graphical program code within the implementation of the graphical program. Executing the graphical program may include executing the multiple instances, e.g., concurrently and/or serially.

Abstract: System and method for debugging a graphical program. A graphical program may be received, e.g., from storage, from another process or device, etc. The program includes parallel graphical program portions, each portion including a graphical program structure and/or an execution path in the graphical program. A first graphical program portion of the parallel graphical program portions may be single step debugged, including executing the single step in the first graphical program portion, and executing, in the background, code in each of the other graphical program portions that is scheduled to execute between start and end of the single step in the first graphical program portion.

Abstract: System and method for creating a graphical program. A first replication structure may be included in a graphical program, where the first replication structure specifies replication of any graphical program code inside the first replication structure. First graphical program code may be included inside the first replication structure. An implementation of the graphical program may be automatically generated, including generating multiple instances of an implementation of the first graphical program code within the implementation of the graphical program. Executing the graphical program may include executing the multiple instances, e.g., concurrently and/or serially.

Abstract: System and method for debugging a graphical program. A graphical program may be received, e.g., from storage, from another process or device, etc. The program includes parallel graphical program portions, each portion including a graphical program structure and/or an execution path in the graphical program. A first graphical program portion of the parallel graphical program portions may be single step debugged, including executing the single step in the first graphical program portion, and executing, in the background, code in each of the other graphical program portions that is scheduled to execute between start and end of the single step in the first graphical program portion.

Abstract: System and method for specifying and implementing relative hardware clocking in a high level programming language. User input specifying a program may be received. The program is specified for deployment to a programmable hardware element (PHE), and includes first and second code portions configured to communicate with each other during execution. The user input may further specify a rational ratio of respective execution rates for the first and second code portions. A hardware configuration program (HCP) implementing the specified program is automatically generated, including automatically determining a respective clock rate for at least one of the first and second code portions based on the rational ratio. The HCP may be deployable to the PHE, including implementing first and second clocks for controlling execution of the first and second code portions in accordance with the rational ratio and the automatically determined respective clock rate for the at least one code portion.

Abstract: System and method for specifying and implementing relative hardware clocking in a high level programming language. User input specifying a program may be received. The program is specified for deployment to a programmable hardware element (PHE), and includes first and second code portions configured to communicate with each other during execution. The user input may further specify a rational ratio of respective execution rates for the first and second code portions. A hardware configuration program (HCP) implementing the specified program is automatically generated, including automatically determining a respective clock rate for at least one of the first and second code portions based on the rational ratio. The HCP may be deployable to the PHE, including implementing first and second clocks for controlling execution of the first and second code portions in accordance with the rational ratio and the automatically determined respective clock rate for the at least one code portion.

Abstract: System and method for managing and specifying hardware implementation of a graphical program. A graphical program that implements an algorithm is stored in a memory of a computer system. The graphical program meets one or more first specified implementation requirements and is targeted for deployment to a programmable hardware element. A plurality of sets of descriptive directives are also stored in the memory, where the descriptive directives are associated with the graphical program and specify one or more additional specified implementation requirements, e.g., memory resource implementations, optimization directives, and so forth, where the additional directives result from programmatic and/or user-specification. Each set of descriptive directives is useable by a synthesis tool to generate a respective hardware configuration program for deployment to the graphical programmable hardware element.