Patents by Inventor Julian J. Sanchez

Julian J. Sanchez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6281062
    Abstract: A novel high-speed, highly reliable VSLI manufacturable metal oxide semiconductor transistor with self-aligned punchthrough stops. A gate insulating layer is formed on a substrate having a first concentration of a first conductivity type. An inner gate electrode of a predetermined length and width is formed on the gate insulating layer. The inner gate electrode has laterally opposite sidewalls along the width of the inner gate electrode. A first and second punchthrough stop regions of a second concentration of the first conductivity type wherein the second concentration is greater than the first concentration, are disposed in the substrate in alignment with the laterally opposite sidewalls of the inner gate electrode. A pair of conductive spacers adjacent to and in electrical contact with respective laterally opposite sidewalls of the inner gate electrode are formed on the gate insulating layer of the transistor. The conductive spacers, along with the inner gate electrode, form a MOSFET gate electrode.
    Type: Grant
    Filed: June 16, 1998
    Date of Patent: August 28, 2001
    Assignee: Intel Corporation
    Inventor: Julian J. Sanchez
  • Patent number: 6081010
    Abstract: A novel high-speed, highly reliable VLSI manufacturable metal oxide semiconductor transistor with self-aligned punchthrough stops. A gate insulating layer is formed on a substrate having a first concentration of a first conductivity type. An inner gate electrode of a predetermined length and width is formed on the gate insulating layer. The inner gate electrode has laterally opposite sidewalls along the width of the inner gate electrode. A first and second punchthrough stop regions of a second concentration of the first conductivity type wherein the second concentration is greater than the first concentration, are disposed in the substrate in alignment with the laterally opposite sidewalls of the inner gate electrode. A pair of conductive spacers adjacent to and in electrical contact with respective laterally opposite sidewalls of the inner gate electrode are formed on the gate insulating layer of the transistor. The conductive spacers, along with the inner gate electrode, form a MOSFET gate electrode.
    Type: Grant
    Filed: February 28, 1994
    Date of Patent: June 27, 2000
    Assignee: Intel Corporation
    Inventor: Julian J. Sanchez
  • Patent number: 5583067
    Abstract: A high speed submicron metal-oxide-semiconductor transistor which exhibits a high immunity to hot electron degradation, good performance, and excellent punchthrough characteristics. An inverse T gate comprising an upper member and a lower member is formed on a well of a first conductivity type. A gate insulating layer is formed between the composite gate and the well. A pair of first conductivity type punchthrough stop regions are formed apart in the well in alignment with the laterally opposite sides of the upper gate member. A first oxide sidewall spacer is formed adjacent to laterally opposite sidewalls of the upper gate member on the lower gate member. A first pair of source/drain regions of a second conductivity type are formed in alignment with the first oxide sidewall spacers. A second sidewall spacer is formed adjacent to each of the first sidewall spacers on the lower gate member.
    Type: Grant
    Filed: February 16, 1996
    Date of Patent: December 10, 1996
    Assignee: Intel Corporation
    Inventor: Julian J. Sanchez