Abstract: A multilevel logic gate for processing digital data in a semiconductor application is provided. The multilevel logic gate comprises, two or more signal input leads for receiving signal input, two or more signal output leads for outputting signal results and a symmetrical structure of an even number of transistor circuit pairs for combining and amplifying the input signals, the symmetrical structure directly interfacing the input leads. The symmetrical structure causes any input signal to propagate through the structure to output at a same latency as any other input signal to the structure.

Abstract: A multilevel logic gate for processing digital data in a semiconductor application is provided. The multilevel logic gate comprises, two or more signal input leads for receiving signal input, two or more signal output leads for outputting signal results and a symmetrical structure of an even number of transistor circuit pairs for combining and amplifying the input signals, the symmetrical structure directly interfacing the input leads. The symmetrical structure causes any input signal to propagate through the structure to output at a same latency as any other input signal to the structure.

Abstract: A multiplexor circuit for performing time-division-multiplexing comprises two or more input signal pairs comprising individual signal lines for providing timed data input into the multiplexor circuit, the pairs alternately selectable for operation, two or more select lines for selecting alternate ones of the input signal pairs during operation, one or more output lines comprising signal output of the circuit and two or more resistive output loads and associated electronic gates. When a specific input pair is not selected for output, the not-selected input pair is not directly connected to the output lines of the circuit but is instead connected to individual ones of the resistive output loads enabled by the associated gates.

Abstract: A multiplexor circuit for performing time-division-multiplexing comprises two or more input signal pairs comprising individual signal lines for providing timed data input into the multiplexor circuit, the pairs alternately selectable for operation, two or more select lines for selecting alternate ones of the input signal pairs during operation, one or more output lines comprising signal output of the circuit and two or more resistive output loads and associated electronic gates. When a specific input pair is not selected for output, the not-selected input pair is not directly connected to the output lines of the circuit but is instead connected to individual ones of the resistive output loads enabled by the associated gates.

Abstract: Nozzles for discharging high velocity air are positioned on either side of an aircraft engine exhaust duct exit. High velocity air is discharged tangential to an outer surface of each nozzle and follows the contour thereof. The nozzles are positioned so that when the high velocity air separates from the outer surface of the respective nozzles, it flows outwardly relative to the aircraft's fuselage structure. The high velocity air from the nozzle closest to the aircraft's fuselage structure impinges on the exhaust gas stream, deflecting the stream away from the fuselage. The high velocity air from the nozzle furthest from the fuselage creates a low pressure area which deflects the exhaust gas stream away from the fuselage. In combination, the two nozzles deflect the exhaust gas stream away from the fuselage to a significant degree.