Patents by Inventor Julian Treu

Julian Treu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240174690
    Abstract: The present invention encompasses compounds of formula (I) wherein R1a, R1b, R2a, R2b, Z, R3 to R5, A, p, U, V and W have the meanings given in the claims and specification, their use as inhibitors of KRAS, pharmaceutical compositions and preparations containing such compounds and their use as medicaments/medical uses, especially as agents for treatment and/or prevention of oncological diseases.
    Type: Application
    Filed: May 9, 2023
    Publication date: May 30, 2024
    Inventors: Joachim BROEKER, Jason ABBOTT, Jianwen CUI, Stephen W. FESIK, Julian FUCHS, Andreas GOLLNER, Lorenz HERDEIS, Tim HODGES, Andrew LITTLE, Andreas MANTOULIDIS, Jason PHAN, Juergen RAMHARTER, Dhruba SARKAR, Christian Alan Paul SMETHURST, Kevin SOKOL, Heinz STADTMUELLER, Qi SUN, Matthias TREU, Alex WATERSON, Birgit WILDING, Tobias WUNBERG
  • Publication number: 20240112993
    Abstract: A semiconductor device comprises a leadframe comprising a die pad and a plurality of leads, a semiconductor die disposed on the die pad, the semiconductor die including a contact pad on a first main face thereof, and one or more bond wires connected with the contact pad, wherein a lead of the plurality of leads is bent back and connected with at least one first bond wire of the one or more bond wires.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 4, 2024
    Inventors: Stefan Schwab, Julian Treu
  • Publication number: 20240030148
    Abstract: A semiconductor device and method is disclosed. In one example, the semiconductor device includes a single first row of leads and a first chip carrier comprising a first electrically insulating layer arranged on the single first row of leads. At least one first semiconductor chip is mounted on the first electrically insulating layer, wherein the at least one first semiconductor chip is arranged over only the single first row of leads.
    Type: Application
    Filed: July 25, 2023
    Publication date: January 25, 2024
    Applicant: Infineon Technologies AG
    Inventors: Kok Kiat KOO, So Seetharam GOBALAKRISNAN, Jürgen SCHREDL, Julian TREU, Dexter Inciong REYNOSO
  • Publication number: 20230093341
    Abstract: A semiconductor package comprising a substrate, at least one semiconductor die disposed on the substrate, at least one electrical connector connected with the semiconductor die, an encapsulant covering the substrate, the at least one semiconductor die, and at least partially the electrical connector, the encapsulant comprising a recess formed into a main surface of the encapsulant, wherein the at least one electrical connector is exposed within the recess.
    Type: Application
    Filed: September 21, 2022
    Publication date: March 23, 2023
    Inventors: Julian Treu, Ivan Nikitin, Bernd Schmoelzer