Abstract: A process is disclosed for simultaneously fabricating bipolar and complementary field effect transistors. The process includes the fabrication of buried layers 18 doped with both phosphorus and arsenic to permit a shorter diffusion time while simultaneously providing buried layers having low resistance and high diffusivity. The process enables fabrication of BiCMOS structures using only six masks prior to the contact mask. The process also comprises oxidizing an epitaxial layer for forming a differential thickness oxide layer which is thicker over the source and drain regions, the collector contact and the emitter than over the base contact region.

Abstract: A process is disclosed for simultaneously fabricating bipolar and complementary field effect transistors. The process includes the fabrication of buried layers 18 doped with both phosphorus and arsenic to permit a shorter diffusion time while simultaneously providing buried layers having low resistance and high diffusivity. The process enables fabrication of BiCMOS structures using only six masks prior to the contact mask.

Abstract: A CMOS and bipolar fabrication process wherein a silicon dioxide layer initially formed over a silicon substrate is etched for forming separate collector and base/emitter regions for a bipolar device, and PMOS and NMOS regions for corresponding PMOS and NMOS devices. Buried layer implants are performed using a minimum number of masks, and then an epitaxial layer is grown over the exposed portions of the silicon substrate. The silicon dioxide walls between the devices provide full dielectric isolation between the devices, as well as between the collector and base/emitter regions of the bipolar device. Nonetheless, the oxide wall between the collector and base/emitter of the bipolar device is sufficiently small to allow the buried layer implants to joint under the wall for forming a conventional buried layer for the bipolar device. Because of the oxide walls, the minimum distance between devices may be 0.5 microns or less.

Abstract: A process is disclosed for simultaneously fabricating bipolar and complementary field effect transistors. The process enables distinguishing the bipolar devices from the CMOS devices with a single base mask 108, while requiring only a single additional mask 114 to define the bipolar emitter and MOS gates. The process forms the gate oxide 100 for the MOS devices at an early stage, then protects that oxide with polysilicon 103 during subsequent fabrication steps. Self-aligned metal silicide contacts 137 are separated from undesired regions using sidewall oxidation techniques.

Abstract: A method and device are disclosed for reducing the circuit size of a class of circuits including many memory cells and logic circuits. Selected drain to bulk or source to bulk transistor junctions are made leaky. The leaky junctions perform their intended (non-leaky) functions as well as the functions of certain other circuit elements. These other elements may therefore be eliminated from the circuit.

Abstract: The present invention provides a silicon gate FET and associated integrated circuit structure in which a second level of polysilicon is selectively oxidized to provide insulating regions where desired. Regions of the polysilicon which were not oxidized are suitably doped to function as electrical interconnects to the source and drain regions in the substrate and to the gate. In the preferred embodiment, a metallic interconnection is made between the gate and drain or source region with the second level of polysilicon.

Abstract: The diffusivity of an impurity in a layer of polycrystalline silicon is controlled by forming the polycrystalline silicon on a thin nucleating layer of polycrystalline silicon possessing a maximum {110} texture.