Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. The data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. In one aspect of an embodiment of the invention, the messaging network connects to a high-bandwidth star-topology serial bus such as a PCI express (PCIe) interface capable of supporting multiple high-bandwidth PCIe lanes. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract: An improved approach is described for implementing a clock management system. A multi-part phase locked loop circuit is provided to handle the different clock needs of the circuit, where each of the phase locked loops within the multi-part phase locked loop circuit may feed a clock output to one or more divider circuits. The divider circuits may be dedicated to specific components. For example, a SoC PLL may generate a clock output to a SoC divider that is dedicated to providing a clock to content address memory (CAM) components. This approach allows the clock management system to efficiently generate clock signals with variable levels of frequencies, even for complicated circuits having many different functional portions and components.

Abstract: Disclosed is an approach for configuring devices for a multiprocessor system, where the devices pertaining to the different processors are viewed as connecting to a standardized common bus. Regardless of the specific processor to which a device is directly connected, that device can be generally identified and accessed along the standardized common bus. PCIe is an example of a suitable standardized bus type that can be employed, where the devices for each processor node are represented as PCIe devices. Therefore, each of the devices would appear to the system software as a PCIe device. A PCIe controller can then be used to access the device by referring to the appropriate device identifier. This permits any device to be accessed on any of the processor nodes, without separate and individualized configurations or drivers for each separate processor node.

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. The data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. In one aspect of an embodiment of the invention, the messaging network connects to a high-bandwidth star-topology serial bus such as a PCI express (PCIe) interface capable of supporting multiple high-bandwidth PCIe lanes. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract: An improved approach is described for implementing a clock management system. A multi-part phase locked loop circuit is provided to handle the different clock needs of the circuit, where each of the phase locked loops within the multi-part phase locked loop circuit may feed a clock output to one or more divider circuits. The divider circuits may be dedicated to specific components. For example, a SoC PLL may generate a clock output to a SoC divider that is dedicated to providing a clock to content address memory (CAM) components. This approach allows the clock management system to efficiently generate clock signals with variable levels of frequencies, even for complicated circuits having many different functional portions and components.