Abstract: Within a data processing systems supporting conditional write processing operations, a trash register is provided such that when non-write conditions are encountered a register write is made to the trash register rather than the data register specified by the conditional write operation. Thus the power signature associated with whether or not a register write does or does not occur is masked. The trash register activity may be programmable enabled and disabled by a configuration parameter stored within a system configuration register.

Abstract: Within a multi-processing system including a plurality of processor cores 4, 6 operating in accordance with coherent multi-processing, each of the cores includes a cache memory 10, 12 storing local copies of data values from a coherent memory region. The respective processor cores may be placed into a power saving mode in which they are non-operative whilst the cache memory remains responsive to coherency management requests such that the system as a whole can continue to operate and manage coherency.

Abstract: Within a coherent multi-processing system multiple processor cores 4, 6 are coupled via respective memory buses to a memory access control unit 16. The memory buses are formed of a uni-processing portion containing signals specifying a memory access request in accordance with a uni-processing protocol. This uni-processing bus is augmented by a multi-processing bus containing signals giving additional information concerning memory access requests which may be used by the memory access control unit to service those requests and manage coherency within the system.