Patents by Inventor Julie Lam

Julie Lam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • IC package design and methodology to compensate for die-substrate CTE mismatch at reflow temperatures
    Patent number: 11495568
    Abstract: An IC package including an integrated circuit die having a major surface and one or more solder bumps located on the major surface in at least one corner region of the major surface and a substrate having a surface, the surface including bump pads thereon. The major surface of the integrated circuit die faces the substrate surface, the one or more solder bumps are bonded to individual ones of the bump pads to thereby form a bond joint, the major surface of the integrated circuit die has a footprint area of at least about 400 mm2. A ratio of a coefficient of thermal expansion of the substrate (CTEsub) to a coefficient of thermal expansion of the integrated circuit die (CTEdie) is at least about 3:1. A method of manufacturing an IC package is also disclosed.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: November 8, 2022
    Assignee: NVIDIA Corporation
    Inventors: Jayprakash Chipalkatti, Zuhair Bokharey, Don Templeton, Brian Schieck, Julie Lam, Prashant Pathak
  • IC PACKAGE DESIGN AND METHODOLOGY TO COMPENSATE FOR DIE-SUBSTRATE CTE MISMATCH AT REFLOW TEMPERATURES
    Publication number: 20210151403
    Abstract: An IC package including an integrated circuit die having a major surface and one or more solder bumps located on the major surface in at least one corner region of the major surface and a substrate having a surface, the surface including bump pads thereon. The major surface of the integrated circuit die faces the substrate surface, the one or more solder bumps are bonded to individual ones of the bump pads to thereby form a bond joint, the major surface of the integrated circuit die has a footprint area of at least about 400 mm2. A ratio of a coefficient of thermal expansion of the substrate (CTEsub) to a coefficient of thermal expansion of the integrated circuit die (CTEdie) is at least about 3:1. A method of manufacturing an IC package is also disclosed.
    Type: Application
    Filed: January 22, 2021
    Publication date: May 20, 2021
    Inventors: Jayprakash Chipalkatti, Zuhair Bokharey, Don Templeton, Brian Schieck, Julie Lam, Prashant Pathak
  • IC package design and methodology to compensate for die-substrate CTE mismatch at reflow temperatures
    Patent number: 10943882
    Abstract: An IC package including an integrated circuit die having a major surface and one or more solder bumps located on the major surface in at least one corner region of the major surface and a substrate having a surface, the surface including bump pads thereon. The major surface of the integrated circuit die faces the substrate surface, the one or more solder bumps are bonded to individual ones of the bump pads to thereby form a bond joint, the major surface of the integrated circuit die has a footprint area of at least about 400 mm2. A ratio of a coefficient of thermal expansion of the substrate (CTEsub) to a coefficient of thermal expansion of the integrated circuit die (CTEdie) is at least about 3:1. A method of manufacturing an IC package is also disclosed.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: March 9, 2021
    Assignee: Nvidia Corporation
    Inventors: Jayprakash Chipalkatti, Zuhair Bokharey, Don Templeton, Brian Schieck, Julie Lam, Prashant Pathak
  • IC PACKAGE DESIGN AND METHODOLOGY TO COMPENSATE FOR DIE-SUBSTRATE CTE MISMATCH AT REFLOW TEMPERATURES
    Publication number: 20210066227
    Abstract: An IC package including an integrated circuit die having a major surface and one or more solder bumps located on the major surface in at least one corner region of the major surface and a substrate having a surface, the surface including bump pads thereon. The major surface of the integrated circuit die faces the substrate surface, the one or more solder bumps are bonded to individual ones of the bump pads to thereby form a bond joint, the major surface of the integrated circuit die has a footprint area of at least about 400 mm2. A ratio of a coefficient of thermal expansion of the substrate (CTEsub) to a coefficient of thermal expansion of the integrated circuit die (CTEdie) is at least about 3:1. A method of manufacturing an IC package is also disclosed.
    Type: Application
    Filed: August 28, 2019
    Publication date: March 4, 2021
    Inventors: Jayprakash Chipalkatti, Zuhair Bokharey, Don Templeton, Brian Schieck, Julie Lam, Prashant Pathak