Abstract: If a consumer instruction specifies a 64 bit source register comprised of results provided by two 32 bit producer instructions, the number of dependencies that must be tracked per source register can be decreased by transforming one or more of the 32 bit producer instructions so that rather than simply storing its result in a 32 bit destination register, the transformed instruction stores its result into a 64 bit logical register along with another 32 bit value held in another 32 bit register.

Abstract: The present invention provides methods and memory structures for efficient tracking and recycling of physical register assignments. The disclosed methods and memory structures each provide an approach to reduce the size of the memory structures needed to track the usage of the physical registers and the recycling of these registers.

Abstract: A method and apparatus is provided for restoring a free physical register list to its previous state without having to physically restore any data. The method and semiconductor device utilizes sets of pointers to manage physical register pointers in the physical register list. The physical register list is able to independently track physical registers for multiple threads of a multithreading microprocessor.

Abstract: A superscalar processor having a content addressable memory structure that transmits a first and second output signal is presented. The superscalar processor performs out of order processing on an instruction set. From the first output signal, the dependencies between currently fetched instructions of the instruction set and previous in-flight instructions can be determined and used to generate a dependency matrix for all in-flight instructions. From the second output signal, the physical register addresses of the data required to execute an instruction, once the dependencies have been removed, may be determined.

Abstract: A memory array includes a plurality of memory cells logically arranged in M rows and N columns, wherein N is the number of memory cells per word of digital information and M is the number of words within the array. A plurality of N data output lines are associated with each of the N columns of the array for selectively retrieving output data from a word located at a predetermined word address in the array. Each data output line is selectively shared by each of the M memory cells within its associated column. Each of the cell output lines of the M memory cells in each of the N columns are logically OR-ed together to provide the output data retrieved by each data output line associated with each of the N columns.

Abstract: A memory cell is provided to store a speculative data value until either a later speculative data value is generated or until the stored speculative data is determined to be the desired data, e.g. no longer speculative. At such time, the invention allows the stored speculative data to quickly and easily be stored as permanent data and further speculative data values to be stored.

Abstract: An electronic memory system includes a memory array including a plurality of memory cells each storing a bit of digital information. Each memory cell is from among a group of cells associated with a word address and communicates with a read enable line for activating the group of cells associated with the word address for data retrieval during a read operation. Further, each cell communicates with at least one data output line shared by other cells from among other word addresses for data retrieval from the group of cells associated with the enabled word address during a read operation. Logic is provided for logically OR-ing together bits of digital information retrieved from cells sharing the same data output line during a read operation in order to prevent damage to the memory array or corruption of data stored therein should enablement signals accidentally be sent simultaneously to a plurality of word addresses. Preferably, the system includes dynamic logic to perform the logical OR operation.

Abstract: A method and apparatus is provided for restoring a free physical register list to its previous state without having to physically restore any data. The method and semiconductor device utilizes sets of pointers to manage physical register pointers in the physical register list. The physical register list is able to independently track physical registers for multiple threads of a multithreading microprocessor.

Abstract: The present invention provides memory structures for efficient tracking and recycling of physical register assignments. This approach reduces the size of the memory structures needed to track the usage of physical registers and the recycling of these registers.

Abstract: A memory cell is provided to store a speculative data value until either a later speculative data value is generated or until the stored speculative data is determined to be the desired data, e.g. no longer speculative. At such time, the invention allows the stored speculative data to quickly and easily be stored as permanent data and further speculative data values to be stored.