Patents by Inventor Julie M. Walker
Julie M. Walker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10936418Abstract: Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.Type: GrantFiled: June 18, 2019Date of Patent: March 2, 2021Assignee: Intel CorporationInventors: Kiran Pangal, Prashant S. Damle, Rajesh Sundaram, Shekoufeh Qawami, Julie M. Walker, Doyle Rivers
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Publication number: 20190370112Abstract: Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.Type: ApplicationFiled: June 18, 2019Publication date: December 5, 2019Inventors: Kiran PANGAL, Prashant S. DAMLE, Rajesh SUNDARAM, Shekoufeh QAWAMI, Julie M. WALKER, Doyle RIVERS
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Patent number: 10324793Abstract: Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.Type: GrantFiled: March 1, 2018Date of Patent: June 18, 2019Assignee: Intel CorporationInventors: Kiran Pangal, Prashant S. Damle, Rajesh Sundaram, Shekoufeh Qawami, Julie M. Walker, Doyle Rivers
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Patent number: 10289597Abstract: Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system.Type: GrantFiled: May 9, 2018Date of Patent: May 14, 2019Assignee: Micron Technology, Inc.Inventors: Doyle Rivers, Paul D. Ruby, Anand S. Ramalingam, Rajesh Sundaram, Julie M. Walker
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Publication number: 20180329854Abstract: Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system.Type: ApplicationFiled: May 9, 2018Publication date: November 15, 2018Inventors: Doyle Rivers, Paul D. Ruby, Anand S. Ramalingam, Rajesh Sundaram, Julie M. Walker
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Publication number: 20180253355Abstract: Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.Type: ApplicationFiled: March 1, 2018Publication date: September 6, 2018Inventors: Kiran PANGAL, Prashant S. DAMLE, Rajesh SUNDARAM, Shekoufeh QAWAMI, Julie M. WALKER, Doyle RIVERS
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Patent number: 10062444Abstract: An integrated circuit, that may be a part of an electronic system, may include a first set of storage cells to store settings and a second set of storage cells to store alternate settings. At least one control cell may also be included in the integrated circuit. The at least one control cell may indicate whether to use the settings stored in the first set of storage cells, or the alternate settings stored in the second set of storage cells, to control one or more operating parameters of the integrated circuit. Methods for using the alternate setting are also described.Type: GrantFiled: February 8, 2016Date of Patent: August 28, 2018Assignee: Intel CorporationInventors: Julie M. Walker, Doyle Rivers
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Patent number: 10056139Abstract: Apparatus, systems, and methods to correct for threshold voltage drift in non-volatile memory devices are disclosed and described. In one example, a compensated demarcation voltage is generated by either a time-based drift compensation scheme or a disturb-based drift compensation scheme, and read and write operations to the non-volatile memory are carried out using the compensated voltage threshold.Type: GrantFiled: July 10, 2017Date of Patent: August 21, 2018Assignee: Intel CorporationInventors: Shekoufeh Qawami, Rajesh Sundaram, Prashant S. Damle, Doyle Rivers, Julie M. Walker
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Patent number: 9996496Abstract: Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system.Type: GrantFiled: August 24, 2017Date of Patent: June 12, 2018Assignee: Micron Technology, Inc.Inventors: Doyle Rivers, Paul D. Ruby, Anand S. Ramalingam, Rajesh Sundaram, Julie M. Walker
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Patent number: 9934088Abstract: Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.Type: GrantFiled: September 3, 2015Date of Patent: April 3, 2018Assignee: Intel CorporationInventors: Kiran Pangal, Prashant S. Damle, Rajesh Sundaram, Shekoufeh Qawami, Julie M. Walker, Doyle Rivers
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Publication number: 20170372780Abstract: Apparatus, systems, and methods to correct for threshold voltage drift in non-volatile memory devices are disclosed and described. In one example, a compensated demarcation voltage is generated by either a time-based drift compensation scheme or a disturb-based drift compensation scheme, and read and write operations to the non-volatile memory are carried out using the compensated voltage threshold.Type: ApplicationFiled: July 10, 2017Publication date: December 28, 2017Applicant: Intel CorporationInventors: Shekoufeh Qawami, Rajesh Sundaram, Prashant S. Damle, Doyle Rivers, Julie M. Walker
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Publication number: 20170351637Abstract: Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system.Type: ApplicationFiled: August 24, 2017Publication date: December 7, 2017Inventors: Doyle Rivers, Paul D. Ruby, Anand S. Ramalingam, Rajesh Sundaram, Julie M. Walker
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Patent number: 9785603Abstract: Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system.Type: GrantFiled: July 18, 2016Date of Patent: October 10, 2017Assignee: Micron Technology, Inc.Inventors: Doyle Rivers, Paul D. Ruby, Anand S. Ramalingam, Rajesh Sundaram, Julie M. Walker
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Patent number: 9721657Abstract: Apparatus, systems, and methods to correct for threshold voltage drift in non-volatile memory devices are disclosed and described. In one example, a compensated demarcation voltage is generated by either a time-based drift compensation scheme or a disturb-based drift compensation scheme, and read and write operations to the non-volatile memory are carried out using the compensated voltage threshold.Type: GrantFiled: April 2, 2016Date of Patent: August 1, 2017Assignee: Intel CorporationInventors: Shekoufeh Qawami, Rajesh Sundaram, Prashant S. Damle, Doyle Rivers, Julie M. Walker
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Publication number: 20160328353Abstract: Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system.Type: ApplicationFiled: July 18, 2016Publication date: November 10, 2016Inventors: Doyle Rivers, Paul D. Ruby, Anand S. Ramalingam, Rajesh Sundaram, Julie M. Walker
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Patent number: 9477616Abstract: Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system.Type: GrantFiled: August 7, 2013Date of Patent: October 25, 2016Assignee: Micron Technology, Inc.Inventors: Doyle Rivers, Paul D. Ruby, Anand S. Ramalingam, Rajesh Sundaram, Julie M. Walker
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Publication number: 20160260499Abstract: An integrated circuit, that may be a part of an electronic system, may include a first set of storage cells to store settings and a second set of storage cells to store alternate settings. At least one control cell may also be included in the integrated circuit. The at least one control cell may indicate whether to use the settings stored in the first set of storage cells, or the alternate settings stored in the second set of storage cells, to control one or more operating parameters of the integrated circuit. Methods for using the alternate setting are also described.Type: ApplicationFiled: February 8, 2016Publication date: September 8, 2016Applicant: Intel CorporationInventors: Julie M. Walker, Doyle Rivers
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Publication number: 20160188409Abstract: Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.Type: ApplicationFiled: September 3, 2015Publication date: June 30, 2016Applicant: INTEL CORPORATIONInventors: Kiran Pangal, Prashant S. Damle, Rajesh Sundaram, Shekoufeh Qawami, Julie M. Walker, Doyle Rivers
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Patent number: 9257162Abstract: An integrated circuit, that may be a part of an electronic system, may include a first set of storage cells to store settings and a second set of storage cells to store alternate settings. At least one control cell may also be included in the integrated circuit. The at least one control cell may indicate whether to use the settings stored in the first set of storage cells, or the alternate settings stored in the second set of storage cells, to control one or more operating parameters of the integrated circuit. Methods for using the alternate setting are also described.Type: GrantFiled: June 18, 2012Date of Patent: February 9, 2016Assignee: Intel CorporationInventors: Julie M. Walker, Doyle Rivers
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Patent number: 9136873Abstract: Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.Type: GrantFiled: March 11, 2013Date of Patent: September 15, 2015Assignee: Intel CorporationInventors: Kiran Pangal, Prashant S. Damle, Rajesh Sundaram, Shekoufeh Qawami, Julie M. Walker, Doyle Rivers