Abstract: Examples disclosed herein relate to determination of a power capping signal based on direct memory access. In an example, a hardware timer in a processor may generate a hardware trigger. In response to the hardware trigger, an analog-to-digital convertor (ADC) engine may obtain an analog voltage signal from a server. ADC engine may convert the analog voltage signal to a digital output. ADC engine may then generate a second hardware trigger. In response to the second hardware trigger, a direct memory access engine may provide the digital output to a programmable logic device via a direct memory access (DMA) operation. The programmable logic device may determine a power capping signal based on the digital output, and provide the power capping signal to the server.

Abstract: Examples disclosed herein relate to determining a power sense output based on a current sense line and a voltage sense line. A first stage circuit has a first voltage input of the current sense line of a server. The first stage circuit also has a feedback voltage input based on an output voltage of the first stage circuit and a variable resistance value based on the voltage sense line of the server. A second stage circuit is used to buffer the first output voltage to yield a second output voltage. A third stage circuit yields a power sense output based on a difference between the second output voltage and the first voltage input.

Abstract: Examples disclosed herein relate to determining a power sense output based on a current sense line and a voltage sense line. A first stage circuit has a first voltage input of the current sense line of a server. The first stage circuit also has a feedback voltage input based on an output voltage of the first stage circuit and a variable resistance value based on the voltage sense line of the server. A second stage circuit is used to buffer the first output voltage to yield a second output voltage. A third stage circuit yields a power sense output based on a difference between the second output voltage and the first voltage input.

Abstract: Examples disclosed herein relate to determination of a power capping signal based on direct memory access. In an example, a hardware timer in a processor may generate a hardware trigger. In response to the hardware trigger, an analog-to-digital convertor (ADC) engine may obtain an analog voltage signal from a server. ADC engine may convert the analog voltage signal to a digital output. ADC engine may then generate a second hardware trigger. In response to the second hardware trigger, a direct memory access engine may provide the digital output to a programmable logic device via a direct memory access (DMA) operation. The programmable logic device may determine a power capping signal based on the digital output, and provide the power capping signal to the server.

Abstract: Example implementations relate to power consumption level adjustment of a computing device. For example, an implementation includes a computing cell and a power subsystem housed in a chassis. A power manager of the power subsystem is to assert an emergency brake signal to a power controller to the computing cell in response to a detection of a power output reduction, to transmit power consumption information to the power controller, and to assert a power restore signal to the power controller. The power controller is to transition a power consumption level of the computing cell from a first level to a second level based on the emergency brake signal, to transition the power consumption level from the second level to a third level based on the power consumption information, and to transition the power consumption level from the third level to the first level based on the power restore signal.