Abstract: An electronic power module includes at least a semiconductor chip having at least one electronic power component and two metal layers between which the semiconductor chip is directly secured. At least a first of the two metal layers forms a redistribution layer having several distinct metal portions, each electrically connected to at least one electrical contact pad of the semiconductor chip, and/or at least one second of the two metal layers includes at least one first structured face arranged against the semiconductor chip and having at least one pad formed in a part of its thickness.

Abstract: A method for producing a semiconductor structure comprises: a) providing a working layer of a semiconductor material; b) providing a carrier substrate of a semiconductor material; c) depositing a thin film of a semiconductor material different from that or those of the working layer and the carrier substrate on a free face to be joined of the working layer and/or the carrier substrate; d) directly joining the free faces of the working layer and the carrier substrate, e) annealing the joined structure at an elevated temperature to bring about segmentation of the encapsulated thin film and form a semiconductor structure comprising an interface region between the working layer and the carrier substrate, the interface region comprising: —regions of direct contact between the working layer and the carrier substrate; and —agglomerates comprising the semiconductor material of the thin film adjacent the regions of direct contact.

Abstract: An electronic device including a stack of a support substrate made of single-crystal SiC having a first surface and of a layer made of single-crystal SiC including a second surface opposite the first surface. The first surface corresponds to a plane of the SiC single crystal of the support substrate and the second surface corresponds to a plane inclined by at least 1° with respect to a plane in the direction of the SiC single crystal of the layer.

Abstract: A electronic device including a stack of a support substrate made of single-crystal SiC having a first surface and of a layer made of single-crystal SiC including a second surface opposite the first surface. The first surface corresponds to a plane of the SiC single crystal of the support substrate and the second surface corresponds to a plane inclined by at least 1° with respect to the plane of the SiC single crystal of the layer.

Abstract: An optoelectronic device includes an array of germanium-based photodiodes including a stack of semiconductor layers, made from germanium, trenches, and a passivation semiconductor layer, made from silicon. Each photodiode includes a silicon-germanium peripheral zone in the semiconductor portion formed through an interdiffusion of the silicon of the passivation semiconductor layer and of the germanium of the semiconductor portion.

Abstract: A process for fabricating an optoelectronic device including an array of germanium-based photodiodes including the following steps: producing a stack of semiconductor layers, made from germanium; producing trenches; depositing a passivation intrinsic semiconductor layer, made from silicon; annealing, ensuring, for each photodiode, an interdiffusion of the silicon of the passivation semiconductor layer and of the germanium of a semiconductor portion, thus forming a peripheral zone of the semiconductor portion, made from silicon-germanium.

Abstract: A process for fabricating an optoelectronic device for emitting infrared radiation, including: i) producing a first stack containing a light source, and a first bonding sublayer made from a metal of interest chosen from gold, titanium and copper, ii) producing a second stack containing a GeSn-based active layer obtained by epitaxy at an epitaxy temperature (Tepi), and a second bonding sublayer made from the metal of interest, iii) determining an assembly temperature (Tc) substantially between an ambient temperature (Tamb) and the epitaxy temperature (Tepi), such that a direct bonding energy per unit area of the metal of interest is higher than or equal to 0.5 J/m2; and iv) joining, by direct bonding, at the assembly temperature (Tc), the stacks.

Abstract: An electronic power module includes at least a semiconductor chip having at least one electronic power component and two metal layers between which the semiconductor chip is directly secured. At least a first of the two metal layers forms a redistribution layer having several distinct metal portions, each electrically connected to at least one electrical contact pad of the semiconductor chip, and/or at least one second of the two metal layers includes at least one first structured face arranged against the semiconductor chip and having at least one pad formed in a part of its thickness.

Abstract: The present disclosure relates to a method of manufacturing a semiconductor device, including the successive steps of: a) forming doped germanium on a germanium layer covering a first support; b) covering said doped germanium with a second support; and c) removing the first support.

Abstract: The present disclosure relates to a method of manufacturing a semiconductor device, including the successive steps of: a) forming doped germanium on a germanium layer covering a first support; b) covering said doped germanium with a second support; and c) removing the first support.

Abstract: A process for fabricating at least one elementary heterostructure includes producing a heterostructure comprising at least one semiconductor structure of resistivity higher than or equal to 1 ?.cm located between two electrically conductive structures of resistivity lower than or equal to 0.1 ?.cm; cutting the heterostructure by electrical discharge machining so as to define at least the elementary heterostructure; the thickness of the semiconductor structure being smaller than about 1/10th of the thickness of at least one of the electrically conductive structures or of the total thickness of the electrically conductive structures.

Abstract: The invention relates to a process for fabricating an optoelectronic device (1) for emitting infrared radiation, comprising the following steps: i) producing a first stack (10) comprising: alight source (11), a first bonding sublayer (17) made from a metal of interest chosen from gold, titanium and copper, ii) producing a second stack (20) comprising: a GeSn-based active layer (23) obtained by epitaxy at an epitaxy temperature (Tepi), a second bonding sublayer (25) made from said metal of interest, iii) determining an assembly temperature (Tc) substantially comprised between an ambient temperature (Tamb) and said epitaxy temperature (Tepi), such that a direct bonding energy per unit area of said metal of interest is higher than or equal to 0.5 J/m2; iv) joining, by direct bonding, at said assembly temperature (Tc), said stacks (10, 20).

Abstract: A process for fabricating an optoelectronic device including an array of germanium-based photodiodes including the following steps: producing a stack of semiconductor layers, made from germanium; producing trenches; depositing a passivation intrinsic semiconductor layer, made from silicon; annealing, ensuring, for each photodiode, an interdiffusion of the silicon of the passivation semiconductor layer and of the germanium of a semiconductor portion, thus forming a peripheral zone of the semiconductor portion, made from silicon-germanium.

Abstract: A process for fabricating at least one elementary heterostructure includes producing a heterostructure comprising at least one semiconductor structure of resistivity higher than or equal to 1 ?·cm located between two electrically conductive structures of resistivity lower than or equal to 0.1 ?·cm; cutting the heterostructure by electrical discharge machining so as to define at least the elementary heterostructure; the thickness of the semiconductor structure being smaller than about 1/10th of the thickness of at least one of the electrically conductive structures or of the total thickness of the electrically conductive structures.

Abstract: An electronic power device including: a first electronic power component in which all the electrodes are arranged at a first main face of the first electronic power component; and an electric contact element in which a first main face is arranged against the first main face of the first electronic power component and which includes plural separate electrically conductive portions to which the electrodes of the first electronic power component are electrically connected. The first electronic power component and the electric contact element together form a stack such that a first lateral face of each of the portions of the electric contact element, substantially perpendicular to the first main face of the electric contact element, is arranged against at least one metallization of a support forming an electric contact of the first electronic power component.

Abstract: Electronic power device comprising: an active layer comprising several lateral and/or semi-lateral components for which the electrodes are located on a front face of the active layer; an interconnection structure comprising several conducting portions to which component electrodes are connected, and located in contact with these electrodes extending parallel to the active layer; a support comprising a front face on which electrically conducting tracks are located, and in which: the interconnection structure is located between the active layer and the support, the conducting portions being placed in contact with the conducting tracks, or the active layer is placed between the interconnection structure and the support, the conducting portions comprising parts extending next to the active layer and connected to the conducting tracks.

Abstract: An electronic power device including: a first electronic power component in which all the electrodes are arranged at a first main face of the first electronic power component; and an electric contact element in which a first main face is arranged against the first main face of the first electronic power component and which includes plural separate electrically conductive portions to which the electrodes of the first electronic power component are electrically connected. The first electronic power component and the electric contact element together form a stack such that a first lateral face of each of the portions of the electric contact element, substantially perpendicular to the first main face of the electric contact element, is arranged against at least one metallization of a support forming an electric contact of the first electronic power component.

Abstract: Electronic power device comprising: an active layer comprising several lateral and/or semi-lateral components for which the electrodes are located on a front face of the active layer; an interconnection structure comprising several conducting portions to which component electrodes are connected, and located in contact with these electrodes extending parallel to the active layer; a support comprising a front face on which electrically conducting tracks are located, and in which: the interconnection structure is located between the active layer and the support, the conducting portions being placed in contact with the conducting tracks, or the active layer is placed between the interconnection structure and the support, the conducting portions comprising parts extending next to the active layer and connected to the conducting tracks.

Abstract: The invention relates to a method for manufacturing a semiconductor on insulator type substrate for radio frequency applications, comprising the following steps in sequence: (a) provision of a silicon substrate with an electrical resistivity of more than 500 Ohm.cm, (b) formation of a polycrystalline silicon layer on the substrate, the method comprising a step between steps a) and b) to form a dielectric material layer, different from a native oxide layer, on the substrate, between 0.5 and 10 nm thick.

Abstract: The invention relates to an electronic chip, comprising: a semiconductor substrate (6) having an active area (8) formed by at least one P doped region and at least one N doped region which form one or more P-N junctions through which most of the useful current flows when said electronic chip is in a conductive state, and at least one channel (44) through which a heat transport coolant can flow, the channel(s) passing through at least said P or N doped region of the active area. Each channel (44) is rectilinear and passes through the substrate (6) in a direction which is collinear with a direction F to the nearest ±45°, where the direction F is perpendicular to the plane of the substrate.