Abstract: A nanomagnetic inductor core that includes: a porous, electrically-insulating template having high-permeability material in the pores thereof to constitute elongated nanowires, and wherein the elongated nanowires are segmented along their axial direction; and a segment of dielectric material interposed between adjacent segments of the high-permeability material along the axial direction of the nanowire; wherein each segment of the high-permeability material has a length, in the axial direction of the nanowire, no greater than a size of a single magnetic domain, and wherein a maximal cross-sectional dimension of the nanowire is no greater than the size of the single magnetic domain. Inductors and LC interposers using such nanomagnetic inductor cores, as well as associated fabrication methods.

Abstract: A method for manufacturing an electrical device that includes: anodizing a portion of an anodizable metal layer so as to obtain an anodic porous oxide region and an anodizable metal region adjoining the anodic porous oxide region, the anodic porous oxide region being thicker than the anodizable metal region; depositing a layer of liner material on the anodic porous oxide region and on the anodizable metal region; depositing a layer of filler material on the layer of liner material to obtain a stacked structure having a top surface; planarizing the stacked structure from a top surface thereof until reaching the layer of the liner material, so as to expose a portion of liner material located above at least a portion of the anodic porous oxide region; and removing the exposed portion of liner material.

Abstract: A capacitor structure that includes a substrate; a conductive layer above the substrate; and a porous layer, above the conductive layer, having pores that extend perpendicularly from a top surface of the porous layer toward the conductive layer. The porous layer comprises a first region in which pores conductive wires are disposed, and a second region in which pores a metal-insulator-metal (MIM) structure is disposed. The first region may be used as a via to contact a bottom electrode of the capacitor structure.

Abstract: An electrical device that includes: a substrate; an anodic porous oxide region above the substrate; a first capacitor electrode region arranged in the anodic porous oxide region, extending in the anodic porous oxide region, the first capacitor electrode region having a first wall perpendicular to the top surface; a second capacitor electrode region arranged in the anodic porous oxide region, extending in the anodic porous oxide region, the second capacitor electrode region having a second wall perpendicular to the top surface and facing the first wall of the first capacitor electrode region, the first wall of the first capacitor electrode region and the second wall of the second capacitor electrode region being separated by a dielectric portion comprising a part of the anodic porous oxide region.

Abstract: A nanowire structure that includes a conductive layer; conductive wires having first ends that contact the conductive layer and second ends that protrude from the conductive layer; and a lateral bridge layer that connects laterally a number of the conductive wires to provide a substantially uniform spacing between the conductive wires.

Abstract: A nanowire array structure having an array of nanopillars located in a well in a material layer. The nanopillars of the array extend in the direction from the well floor towards the well mouth. A hard mask overlies the outer peripheral nanopillars in the array and extends outwards to cover the remainder of the well mouth. An aperture in the hard mask exposes the nanopillars disposed inwardly of the outer peripheral nanopillars. The hard mask planarizes the structure, avoiding formation of large topological features at the periphery of the array of nanopillars, thus facilitating integration of the structure into a semiconductor product. At least some of the outer peripheral nanopillars may be in pores of anodic oxide. There are also disclosed semiconductor products incorporating such nanowire array structures and methods of their fabrication.

Abstract: A semi-conductor structure with selective bottom terminal contacting is described. The semiconductor device comprises a first metal layer disposed over a substrate; a conductive layer disposed over the first metal layer; and a second metal layer disposed over the conductive layer, the second metal layer embedding a porous structure comprising a plurality of pores that extend substantially perpendicularly from a top surface of the porous structure toward the conductive layer, wherein only a subset of the plurality of pores open onto the conductive layer.

Abstract: A substrate that includes a base layer having a first principal surface defining a plurality of first trenches and intervening first lands, and a cover layer provided over the first principal surface of the base layer and covering the first trenches and first lands substantially conformally, wherein the surface of the cover layer remote from the first principal surface of the base layer comprises a plurality of second trenches and intervening second lands defined at a smaller scale than the first trenches and first lands. The substrate may be used to fabricate a capacitive element in which thin film layers are provided and conformally cover the second trenches and second lands of the cover layer, to create a metal-insulator-metal structure having high capacitance density.

Abstract: A nanowire structure is manufactured by forming islands of conductive material on a substrate, and a conductive sacrificial layer in the space between conductive islands. The conductive islands include an anodic etch barrier layer. An anodizable layer is formed, over the conductive islands and sacrificial layer, and anodized to form a porous template. Nanowires are formed in regions of the porous template that overlie the conductive islands. Removal of the porous template and sacrificial layer leaves a nanowire structure including isolated groups of nanowires connected to respective conductive islands which function as current collectors. Respective stacks of conductive and insulator layers are formed over different groups of the nanowires to form respective capacitors that are electrically isolated from one another. A monolithic component may thus be formed including an array of isolated capacitors formed over nanowires.

Abstract: A nanomagnetic inductor core that includes: a porous, electrically-insulating template having high-permeability material in the pores thereof to constitute elongated nanowires, and wherein the elongated nanowires are segmented along their axial direction; and a segment of dielectric material interposed between adjacent segments of the high-permeability material along the axial direction of the nanowire; wherein each segment of the high-permeability material has a length, in the axial direction of the nanowire, no greater than a size of a single magnetic domain, and wherein a maximal cross-sectional dimension of the nanowire is no greater than the size of the single magnetic domain. Inductors and LC interposers using such nanomagnetic inductor cores, as well as associated fabrication methods.

Abstract: A porous region structure and a method of fabrication thereof are disclosed. The porous region structure is characterized by having a hard mask interface region with non-uniform pores sealed and thereby excluded functionally from the structure. The sealing of the hard mask interface region is done using a hard mask deposited on top of an anodization hard mask used to define the porous region of the structure. By excluding the hard mask interface region, the porosity ratio and the equivalent specific surface of the porous region structure can be controlled or quantified with higher accuracy. Corrosion due to exposure of an underlying metal layer of the structure is also significantly reduced by sealing the hard mask interface region.

Abstract: Three-dimensional capacitive structures may be produced by forming a capacitive stack conformally over pores in a region of porous anodic oxide. The porous anodic oxide region is provided on a stack of electrically-conductive layers including an anodization-resistant layer and an interconnection layer. In the pores there is a position having restricted diameter quite close to the pore bottom. In a first percentage of the pores in the region of anodic oxide, a functional portion of the capacitive stack is formed so as to extend into the pores no further than the restricted-diameter position. Cracks that may be present in the anodization-resistant layer have reduced effect on the properties of the capacitive structure. Increased thickness of the anodization-resistant layer can be tolerated, enabling equivalent series resistance of the overall capacitive structure to be reduced.

Abstract: A substrate that includes a base layer having a first principal surface defining a plurality of first trenches and intervening first lands, and a cover layer provided over the first principal surface of the base layer and covering the first trenches and first lands substantially conformally, wherein the surface of the cover layer remote from the first principal surface of the base layer comprises a plurality of second trenches and intervening second lands defined at a smaller scale than the first trenches and first lands. The substrate may be used to fabricate a capacitive element in which thin film layers are provided and conformally cover the second trenches and second lands of the cover layer, to create a metal-insulator-metal structure having high capacitance density.

Abstract: A nanowire structure that includes a conductive layer; conductive wires having first ends that contact the conductive layer and second ends that protrude from the conductive layer; and a lateral bridge layer that connects laterally a number of the conductive wires to provide a substantially uniform spacing between the conductive wires.

Abstract: A substrate that includes a base layer having a first principal surface defining a plurality of first trenches and intervening first lands, and a cover layer provided over the first principal surface of the base layer and covering the first trenches and first lands substantially conformally, wherein the surface of the cover layer remote from the first principal surface of the base layer comprises a plurality of second trenches and intervening second lands defined at a smaller scale than the first trenches and first lands. The substrate may be used to fabricate a capacitive element in which thin film layers are provided and conformally cover the second trenches and second lands of the cover layer, to create a metal-insulator-metal structure having high capacitance density.

Abstract: A porous region structure and a method of fabrication thereof are disclosed. The porous region structure is characterized by having a hard mask interface region with non-uniform pores sealed and thereby excluded functionally from the structure. The sealing of the hard mask interface region is done using a hard mask deposited on top of an anodization hard mask used to define the porous region of the structure. By excluding the hard mask interface region, the porosity ratio and the equivalent specific surface of the porous region structure can be controlled or quantified with higher accuracy. Corrosion due to exposure of an underlying metal layer of the structure is also significantly reduced by sealing the hard mask interface region.

Abstract: A semiconductor device that includes a porous anodic region for embedding a structure. The porous anodic region is defined by a ductile hard mask. The ductility of the hard mask reduces the potential for the hard mask to crack during the formation by anodization of the porous anodic region. The ductile hard mask may be a metal. The metal may be selected to form a stable oxide when exposed to the anodization electrolyte thereby enabling the hard mask to self-repair if a crack occurs during the anodization process.

Abstract: An electronic product having a silicon-on-insulator substrate, a porous layer of anodic oxide or anodic hydroxide over the silicon layer of the silicon-on-insulator substrate, and a metal layer over the porous layer and that defines at least one electrical transmission line. The velocity of the electrical signal in the at least one electrical transmission line may be controlled by appropriate configuration of the porosity ratio of the porous layer.

Abstract: A substrate that includes a base layer having a first principal surface defining a plurality of first trenches and intervening first lands, and a cover layer provided over the first principal surface of the base layer and covering the first trenches and first lands substantially conformally, wherein the surface of the cover layer remote from the first principal surface of the base layer comprises a plurality of second trenches and intervening second lands defined at a smaller scale than the first trenches and first lands. The substrate may be used to fabricate a capacitive element in which thin film layers are provided and conformally cover the second trenches and second lands of the cover layer, to create a metal-insulator-metal structure having high capacitance density.