Abstract: A data storage device comprises a storage array containing first data, a buffer containing RAID units, and a controller in communication with the storage array and the buffer. The controller is configured to receive a read request from a host device for a second data stored in the storage array, and determine an identifier associated with the requested second data. The controller is also configured to determine if the requested second data contains an unrecoverable error. The controller then accumulates first data, including a parity value, contained in the storage array associated with the same identifier as the requested second data in a reconstruction buffer, if the requested second data contains an unrecoverable error.

Abstract: A memory system comprises a nonvolatile memory having a plurality of memory cells and a memory controller for controlling the nonvolatile memory. The plurality of memory cells is divided into different groups, and each group is assigned a threshold read count value from a predetermined range of read count values. The memory controller includes a counter which tracks a read count for each group, a determination circuit configured to compare the read count for each group tracked by the counter to the assigned threshold read count value for the group, and a nonvolatile memory read/write circuit configured to read data from the group when the determination circuit indicates the read count for the group has reached the assigned threshold read count value.

Abstract: A data storage device comprises a nonvolatile semiconductor storage array containing data, a controller in communication with the nonvolatile semiconductor storage array, and a buffer containing RAID units, the RAID units being in communication with the nonvolatile semiconductor storage array via the controller. The controller is configured to receive write requests from a host device, and accumulate first data relating to the write requests in the RAID units. The controller is also configured to, concurrently, transfer the first data contained in the RAID units to the nonvolatile semiconductor storage array, calculate parity values of the first data contained in the RAID units, each parity value relating to each write request, and accumulate the parity values in a context identifier buffer. The controller is further configured to associate context identifiers with the parity values, and store the parity values and the context identifiers in the nonvolatile semiconductor storage array.

Abstract: A solid state drive (SSD) and a method for managing data stored in the SSD is disclosed. In one embodiment, the SSD includes a memory controller and a controller memory buffer within the memory controller. The SSD further includes a host interface communicatively coupled to the memory controller and configured to receive a set of host commands from a host device. A first local processor of the SSD is configured to generate a set of local commands, and a second local processor of the SSD is configured to execute the set of local commands and the set of host commands. The memory controller is configured to store the set of local commands in a first area of the controller memory buffer reserved for the first local processor and to store the set of host commands in a second area of the controller memory buffer reserved for the host device.

Abstract: A memory system includes a memory controller having a bank command scheduler implemented in a hardware logic block and a power budget controller including a power budget register and a credit register. The hardware logic block is able to determine a command in a queue to be transmitted to a memory bank over a channel, estimate a power consumption value for the command, and query the power budget controller to determine if the power consumption value is within a threshold. If the power consumption value is within the threshold, the hardware logic block receives a grant response from the power budget controller, adds the power consumption value to the credit register value, transmits the command over the channel, and transmits a signal to the power budget controller indicating that the command has been executed and that the power consumption value should be subtracted from the credit register value.

Abstract: A data storage device comprises a nonvolatile semiconductor storage array containing data, a controller in communication with the nonvolatile semiconductor storage array, and a buffer containing RAID units, the RAID units being in communication with the nonvolatile semiconductor storage array via the controller. The controller is configured to receive write requests from a host device, and accumulate first data relating to the write requests in the RAID units. The controller is also configured to, concurrently, transfer the first data contained in the RAID units to the nonvolatile semiconductor storage array, calculate parity values of the first data contained in the RAID units, each parity value relating to each write request, and accumulate the parity values in a context identifier buffer. The controller is further configured to associate context identifiers with the parity values, and store the parity values and the context identifiers in the nonvolatile semiconductor storage array.

Abstract: The current consumed by flash memory devices on the channels of a solid-state drive (SSD) device will be in the form of a time varying waveform, characterized mainly by the types of commands being processed, and are often in the form of periods of constant levels interspersed with very short high current peaks or spikes. When multiple commands are being processed, significant high current peak demands and current surges can occur. The invention described herein is a device and method for scheduling commands to be processed in order to reduce the size of peak current demands and current surges. According to one embodiment of the invention, the device and method for scheduling a command uses look-up tables to determine the time to initiate the processing of the command by the flash memory devices.

Abstract: A memory controller implemented within a non-volatile data storage device with improved efficiency for executing data invalidation commands is disclosed. In one embodiment, the non-volatile data storage device in communication with a host device and comprises a processor, a memory device that includes a plurality of physical storage locations, a cache memory configured to store a map table and a count value. The controller is configured to receive a data invalidation request from the host device where the request includes an execution parameter. Based on the execution parameter, the controller executes the invalidation request in an efficient and flexible manner.

Abstract: A data storage device capable of namespace re-sizing comprises a nonvolatile semiconductor storage device containing data accessed via a logical address that includes a namespace identifier and a logical block address, and a controller. The storage device can convert the namespace identifier to a base address using a first look up table. The storage device can further convert the logical block address to namespace allocation units of storage. The storage device can also determine a pointer using the base address, the namespace allocation units, and a second look up table. Further, the storage device can determine a full logical cluster address using the pointer.

Abstract: A solid state drive (SSD) and a method for managing data stored in the SSD is disclosed. In one embodiment, the SSD includes a memory controller and a controller memory buffer within the memory controller. The SSD further includes a host interface communicatively coupled to the memory controller and configured to receive a set of host commands from a host device. A first local processor of the SSD is configured to generate a set of local commands, and a second local processor of the SSD is configured to execute the set of local commands and the set of host commands. The memory controller is configured to store the set of local commands in a first area of the controller memory buffer reserved for the first local processor and to store the set of host commands in a second area of the controller memory buffer reserved for the host device.

Abstract: A mass storage device and method for storing data originally written to a volatile memory with byte level I/O protocol commands to a non-volatile memory using block level I/O protocol commands. The mass storage device includes a host interface for communicating with the host computer system, at least one non-volatile memory, at least one volatile memory, a memory controller configured to accept block level I/O protocol commands from the host computer system to read data from and write data to the non-volatile memory, and additionally accept byte level memory I/O commands from the host computer system for reading data from and writing data to the at least one volatile memory, and means for retrieving the data written by the host computer system using the byte level memory I/O commands from the volatile memory and writing the data retrieved from the volatile memory to the at least one non-volatile memory.

Abstract: A memory controller implemented within a non-volatile data storage device with improved efficiency for executing data invalidation commands is disclosed. In one embodiment, the non-volatile data storage device in communication with a host device and comprises a processor, a memory device that includes a plurality of physical storage locations, a cache memory configured to store a map table and a count value. The controller is configured to receive a data invalidation request from the host device where the request includes an execution parameter. Based on the execution parameter, the controller executes the invalidation request in an efficient and flexible manner.

Abstract: The current consumed by flash memory devices on the channels of a solid-state drive (SSD) device will be in the form of a time varying waveform, characterized mainly by the types of commands being processed, and are often in the form of periods of constant levels interspersed with very short high current peaks or spikes. When multiple commands are being processed, significant high current peak demands and current surges can occur. The invention described herein is a device and method for scheduling commands to be processed in order to reduce the size of peak current demands and current surges. According to one embodiment of the invention, the device and method for scheduling a command uses look-up tables to determine the time to initiate the processing of the command by the flash memory devices.

Abstract: A mass storage device and method for storing data originally written to a volatile memory with byte level I/O protocol commands to a non-volatile memory using block level I/O protocol commands. The mass storage device includes a host interface for communicating with the host computer system, at least one non-volatile memory, at least one volatile memory, a memory controller configured to accept block level I/O protocol commands from the host computer system to read data from and write data to the non-volatile memory, and additionally accept byte level memory I/O commands from the host computer system for reading data from and writing data to the at least one volatile memory, and means for retrieving the data written by the host computer system using the byte level memory I/O commands from the volatile memory and writing the data retrieved from the volatile memory to the at least one non-volatile memory.

Abstract: In a first embodiment of the present invention, a method for allowing a microprocessor to access a flash memory is provided, the method comprising: fetching code instructions and data from the flash memory via a unidirectional code bus coupled to a flash controller, which is coupled to a databus interface, which is coupled to the flash memory; executing the code instructions in a manner that is substantially similar to that as used for a read only memory (ROM) coupled to the microprocessor; and writing data to the flash memory via a bidirectional databus separate from the unidirectional code bus, wherein the bidirectional databus is coupled to the databus interface and to a scratch memory, wherein the writing comprises using write flash procedures located in the ROM, the write flash procedures comprising instructions for reading and using parameter values stored in the scratch memory and for erasing memory locations and writing data to memory locations in the flash memory.

Abstract: In a first embodiment of the present invention, a method for caching in a processor system having virtual memory is provided, the method comprising: monitoring slow memory in the processor system to determine frequently accessed pages; for a frequently accessed page in slow memory: copy the frequently accessed page from slow memory to a location in fast memory; and update virtual address page tables to reflect the location of the frequently accessed page in fast memory.