Patents by Inventor Julien Orlando
Julien Orlando has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240012107Abstract: A first input signal that corresponds to an output transmitted signal of an amplifier of a vehicle radar system is received and a digital threshold signal is transmitted to an input terminal of a digital-to-analog converter. The digital-to-analog converter is configured to generate an analog threshold value that is at least partially determined by a digital threshold value encoded into the digital threshold signal. If it is determined that a magnitude of the first input signal is less than a magnitude of the analog threshold value, a flag signal is transmitted to a system controller. The flag signal is indicative that a power level of the first output signal has fallen below a safety threshold value.Type: ApplicationFiled: October 11, 2022Publication date: January 11, 2024Inventors: Yi YIN, Birama GOUMBALLA, Olivier Vincent DOARE, Julien ORLANDO
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Patent number: 11656330Abstract: Disclosed are various embodiments for improving the accuracy of a phase associated with the radar signal by identifying a spectral signature associated with a radio frequency (RF) impairment and performing digital predistortion to enhance the radar performance and to compensate for the impairment that causes offset or imbalance of the phase rotator output cause signal distortion or otherwise degrade of the phase of the signal. The self-calibrating mechanism of the present disclosure is configured to identify the impairments, determine a spectral signature associated with the impairment, and optimize the phase error through digital predistortion of the RF signal based at least in part on the spectral signature associated with the impairment.Type: GrantFiled: June 17, 2020Date of Patent: May 23, 2023Assignee: NXP USA, Inc.Inventors: Olivier Vincent Doare, Julien Orlando
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Patent number: 11652470Abstract: A phase rotator control circuit is provided. The phase rotator control circuit is coupled to a phase rotator core and includes a first set of transistors coupled to receive digital control signals. The first set of transistors is coupled to a second set of transistors configured and arranged to form a filtered current mirror. An output of the filtered current mirror is coupled to provide an analog phase control signal to the phase rotator core.Type: GrantFiled: March 17, 2021Date of Patent: May 16, 2023Assignee: NXP USA, INC.Inventors: Dominique Delbecq, Julien Orlando
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Patent number: 11496122Abstract: A phase rotator calibration system is provided. The phase rotator calibration system includes a phase rotator portion having input for receiving an input signal and an output for providing an output signal. A calibration portion is coupled to the phase rotator portion. The calibration portion is configured to determine a phase error based on a phase estimation. The phase estimation is generated by way of an arccosine function.Type: GrantFiled: June 29, 2021Date of Patent: November 8, 2022Assignee: NXP USA, Inc.Inventors: Dominique Delbecq, Olivier Vincent Doaré, Julien Orlando
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Publication number: 20220021378Abstract: A phase rotator calibration system is provided. The phase rotator calibration system includes a phase rotator portion having input for receiving an input signal and an output for providing an output signal. A calibration portion is coupled to the phase rotator portion. The calibration portion is configured to determine a phase error based on a phase estimation. The phase estimation is generated by way of an arccosine function.Type: ApplicationFiled: June 29, 2021Publication date: January 20, 2022Inventors: Dominique Delbecq, Olivier Vincent Doaré, Julien Orlando
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Publication number: 20210305969Abstract: A phase rotator control circuit is provided. The phase rotator control circuit is coupled to a phase rotator core and includes a first set of transistors coupled to receive digital control signals. The first set of transistors is coupled to a second set of transistors configured and arranged to form a filtered current mirror. An output of the filtered current mirror is coupled to provide an analog phase control signal to the phase rotator core.Type: ApplicationFiled: March 17, 2021Publication date: September 30, 2021Inventors: Dominique Delbecq, Julien Orlando
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Patent number: 11131762Abstract: A fast chirp Phase Locked Loop with a boosted return time includes a Voltage Controlled Oscillator, VCO, generating a Frequency Modulated Continuous Waveform, FMCW. The VCO responds to a filtered output voltage of a filter connected to a charge pump. A digital controller modifies the FMCW to generate a chirp phase and a return phase. The chirp phase includes a first linear change of the FMCW from a start frequency to a stop frequency. The return phase includes a second linear change of the FMCW from the stop frequency to the start frequency. A boost circuit connects to the digital controller and the filter. The boost circuit supplies a boost current during the return phase. The boost current is proportional to a return slope of the return phase and inversely proportional to a VCO gain of the VCO.Type: GrantFiled: May 30, 2019Date of Patent: September 28, 2021Assignee: NXP USA, INC.Inventors: Jean-Stephane Vigier, Didier Salle, Cristian Pavao-Moreira, Julien Orlando
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Patent number: 11131763Abstract: A fast chirp Phase Locked Loop with a phase preset includes a Voltage Controlled Oscillator, VCO, generating a Frequency Modulated Continuous Waveform, FMCW. The VCO responds to a filtered output voltage of a filter connected to a charge pump. A digital controller modifies the FMCW to generate a chirp phase and a return phase. The chirp phase includes a first linear change of the FMCW from a start frequency to a stop frequency. The return phase includes a second linear change of the FMCW from the stop frequency to the start frequency. A phase preset circuit connects to the digital controller and the filter. The phase preset circuit supplies a phase preset current during a start frequency time preceding the chirp phase. The phase preset current is proportional to a VCO gain of the VCO and inversely proportional to a chirp current during the chirp phase.Type: GrantFiled: May 30, 2019Date of Patent: September 28, 2021Assignee: NXP USA, INC.Inventors: Jean-Stephane Vigier, Didier Salle, Cristian Pavao-Moreira, Julien Orlando
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Patent number: 11054513Abstract: A communication unit (700) is described that includes a plurality of cascaded devices that comprise at least one master device (710) and at least one slave device (720, 723) configured in a master-slave arrangement. The at least one master device (710) and at least one slave device (720, 723) each comprise: an analog-to-digital converter, ADC, (741, 742) configured to use a same re-created system clock signal (788, 790) to align respective sampling instants between each ADC (741, 742). The at least one master device (710) comprises: a clock generation circuit comprising an internally-generated reference phase locked loop circuit (708), configured to output a system clock signal (782, 784); and a modulator circuit (762) coupled to the clock generation circuit and configured to receive and distribute the system clock signal (784).Type: GrantFiled: June 21, 2019Date of Patent: July 6, 2021Assignee: NXP USA, INC.Inventors: Olivier Doaré, Didier Salle, Cristian Pavao Moreira, Julien Orlando, Jean-Stephane Vigier, Andres Barrilado Gonzalez
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Publication number: 20200400783Abstract: Disclosed are various embodiments for improving the accuracy of a phase associated with the radar signal by identifying a spectral signature associated with a radio frequency (RF) impairment and performing digital predistortion to enhance the radar performance and to compensate for the impairment that causes offset or imbalance of the phase rotator output cause signal distortion or otherwise degrade of the phase of the signal. The self-calibrating mechanism of the present disclosure is configured to identify the impairments, determine a spectral signature associated with the impairment, and optimize the phase error through digital predistortion of the RF signal based at least in part on the spectral signature associated with the impairment.Type: ApplicationFiled: June 17, 2020Publication date: December 24, 2020Inventors: Olivier Vincent Doare, Julien Orlando
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Publication number: 20200003862Abstract: A communication unit (900) includes a plurality of cascaded devices that comprise at least one master device (910) and at least one slave device (920, 923) configured in a master-slave arrangement. The at least one master device (910) and at least one slave device (920, 923) each include: a demodulator circuit (964, 965) configured to receive a distributed reference clock signal (984) and re-create a system clock signal (988, 990) therefrom; a clock generation circuit comprising an internally-generated reference phase locked loop configured to receive the re-created system clock signal (988, 990) to create a master-slave clock signal; and an analog-to-digital converter, ADC, (941, 942) coupled to the reference phase locked loop and configured to use a same master-slave clock signal (988, 990) to align respective sampling instants between each ADC (941, 942) of the at least one master device (910) and at least one slave device (920, 923).Type: ApplicationFiled: June 21, 2019Publication date: January 2, 2020Inventors: Olivier Doaré, Didier Salle, Cristian Pavao Moreira, Julien Orlando, Jean-Stephane Vigier, Andres Barrilado Gonzalez
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Publication number: 20200003883Abstract: A communication unit (700) is described that includes a plurality of cascaded devices that comprise at least one master device (710) and at least one slave device (720, 723) configured in a master-slave arrangement. The at least one master device (710) and at least one slave device (720, 723) each comprise: an analog-to-digital converter, ADC, (741, 742) configured to use a same re-created system clock signal (788, 790) to align respective sampling instants between each ADC (741, 742). The at least one master device (710) comprises: a clock generation circuit comprising an internally-generated reference phase locked loop circuit (708), configured to output a system clock signal (782, 784); and a modulator circuit (762) coupled to the clock generation circuit and configured to receive and distribute the system clock signal (784).Type: ApplicationFiled: June 21, 2019Publication date: January 2, 2020Inventors: Olivier Doaré, Didier Salle, Cristian Pavao Moreira, Julien Orlando, Jean-Stephane Vigier, Andres Barrilado Gonzalez
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Publication number: 20190377076Abstract: A fast chirp Phase Locked Loop (70) with a phase preset includes a Voltage Controlled Oscillator, VCO, (12) generating a Frequency Modulated Continuous Waveform, FMCW, (14). The VCO responds to a filtered output voltage (74) of a filter (72) connected to a charge pump (28). A digital controller (82) modifies the FMCW to generate a chirp phase (304) and a return phase (300). The chirp phase includes a first linear change of the FMCW from a start frequency (202) to a stop frequency (204). The return phase includes a second linear change of the FMCW from the stop frequency to the start frequency. A phase preset circuit (86) connects to the digital controller and the filter. The phase preset circuit supplies a phase preset current (98) during a start frequency time (302) preceding the chirp phase. The phase preset current is proportional to a VCO gain of the VCO and inversely proportional to a chirp current during the chirp phase.Type: ApplicationFiled: May 30, 2019Publication date: December 12, 2019Inventors: Jean-Stephane Vigier, Didier Salle, Cristian Pavao-Moreira, Julien Orlando
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Publication number: 20190377078Abstract: A fast chirp Phase Locked Loop (70) with a boosted return time includes a Voltage Controlled Oscillator, VCO, (12) generating a Frequency Modulated Continuous Waveform, FMCW, (14). The VCO responds to a filtered output voltage (74) of a filter (72) connected to a charge pump (28). A digital controller (82) modifies the FMCW to generate a chirp phase (304) and a return phase (300). The chirp phase includes a first linear change of the FMCW from a start frequency (202) to a stop frequency (204). The return phase includes a second linear change of the FMCW from the stop frequency to the start frequency. A boost circuit (86) connects to the digital controller and the filter. The boost circuit supplies a boost current (98) during the return phase. The boost current is proportional to a return slope of the return phase and inversely proportional to a VCO gain of the VCO.Type: ApplicationFiled: May 30, 2019Publication date: December 12, 2019Inventors: Jean-Stephane Vigier, Didier Salle, Cristian Pavao-Moreira, Julien Orlando