Abstract: The block de-interleaving system includes an input for receiving a set of time-aligned blocks or interleaved data, physical memory unit, and a de-interleaving block for writing the blocks in the memory in a first predetermined manner and reading the blocks from the memory in a second predetermined manner to de-interleave the data of the blocks. The physical memory unit may include several different physical memories, and the de-interleaving block is adapted to completely write and read a block into and from one physical elementary memory.

Abstract: A method for de-interleaving S2 received sequences of interleaved received data samples respectively issued from S2 physical channels and to be associated with S1 output transport channels is provided. The S2 received sequences have been delivered, before transmission by a two-stage multi-interleaving device, from S1 initial sequences of ordered data samples respectively associated to S1 initial transport channels. The two-stage multi-interleaving device includes a first stage including S1 interleaving blocks respectively associated to the S1 initial transport channels, a second stage including S2 interleaving blocks respectively associated to the S2 physical channels, and an inter-stage of predetermined data-routing functions connected between the first and second stages.

Abstract: A method for de-interleaving S2 received sequences of interleaved received data samples respectively issued from S2 physical channels and to be associated with S1 output transport channels is provided. The S2 received sequences have been delivered, before transmission by a two-stage multi-interleaving device, from S1 initial sequences of ordered data samples respectively associated to S1 initial transport channels. The two-stage multi-interleaving device includes a first stage including S1 interleaving blocks respectively associated to the S1 initial transport channels, a second stage including S2 interleaving blocks respectively associated to the S2 physical channels, and an inter-stage of predetermined data-routing functions connected between the first and second stages.

Abstract: A method for de-interleaving S2 received sequences of interleaved received data samples respectively issued from S2 physical channels and to be associated with S1 output transport channels is provided. The S2 received sequences have been delivered, before transmission by a two-stage multi-interleaving device, from S1 initial sequences of ordered data samples respectively associated to S1 initial transport channels. The two-stage multi-interleaving device includes a first stage including S1 interleaving blocks respectively associated to the S1 initial transport channels, a second stage including S2 interleaving blocks respectively associated to the S2 physical channels, and an inter-stage of predetermined data-routing functions connected between the first and second stages.

Abstract: A device for processing data to be interleaved and stored in target memories includes N interleaving buffers, N producers, and N cells. Each cell includes a register bank of size W, and a delay circuit. The variable M defines a maximum number of concurrent write operations supported per time step W, and defines a maximum buffer size. These parameters are chosen to reflect a standard case. At any time step, each of the N interleaving buffers receives m log-likelihood ratio (LLR) inputs and writes up to M of these into the register banks. When m is larger than M, m-M producers are delayed by the delay circuit. When a buffer overflow occurs (more than W LLRs values), m producers are delayed by the delay circuit. One LLR value is fetched from the register bank and is written in an SRAM interleaving memory.

Abstract: A system and method is provided for estimating a sequence of N bits ({circumflex over (x)}0{circumflex over (x)}1 . . . {circumflex over (x)}N?1) corresponding to a received sequence of M digital data (r0r1 . . . rM?1). The method includes determining candidate sequences of MRS digital data from a reduced reference sequence space comprising 2NRS reduced reference sequences of MRS reference digital data (s0s1 . . . sMRS?1), MRS being less than M, and 2NRS being less than or equal to 2N. The method further includes making up each candidate sequence with remaining reference symbols to obtain at least one complete candidate sequence of M digital data, and determining the sequence of N bits ({circumflex over (x)}0{circumflex over (x)}1 . . . {circumflex over (x)}N?1) from the complete candidate sequences.

Abstract: Successive sequences of interleaved data samples extracted from a virtual memory having L0 columns and C0 rows are de-interleaved. The de-interleaving includes receiving each sequence of the interleaved data samples, and writing row by row the received sequences of interleaved data samples in a de-interleaving memory array having L rows and C columns, with L being greater or equal to L0 and C being greater or equal to C0. The data samples stored in the de-interleaving memory array are de-interleaved sub-array by sub-array. Each sub-array is a square cluster array having a number SQ of rows and columns. A cluster array is a row of the square cluster array comprising SQ data samples, with the number L of rows and the number C of columns of the de-interleaving memory array being multiples of the number SQ of rows and columns.

Abstract: The block de-interleaving system includes an input for receiving a set of time-aligned blocks or interleaved data, physical memory unit, and a de-interleaving block for writing the blocks in the memory in a first predetermined manner and reading the blocks from the memory in a second predetermined manner to de-interleave the data of the blocks. The physical memory unit may include several different physical memories, and the de-interleaving block is adapted to completely write and read a block into and from one physical elementary memory.

Abstract: A device for processing data to be interleaved and stored in target memories includes N interleaving buffers, N producers, and N cells. Each cell includes a register bank of size W, and a delay circuit. The variable M defines a maximum number of concurrent write operations supported per time step W, and defines a maximum buffer size. These parameters are chosen to reflect a standard case. At any time step, each of the N interleaving buffers receives m log-likelihood ratio (LLR) inputs and writes up to M of these into the register banks. When m is larger than M, m-M producers are delayed by the delay circuit. When a buffer overflow occurs (more than W LLRs values), m producers are delayed by the delay circuit. One LLR value is fetched from the register bank and is written in an SRAM interleaving memory.

Abstract: A system and method is provided for estimating a sequence of N bits ({circumflex over (x)}0{circumflex over (x)}1 . . . {circumflex over (x)}N?1) corresponding to a received sequence of M digital data (r0r1 . . . rM?1). The method includes determining candidate sequences of MRS digital data from a reduced reference sequence space comprising 2NRS reduced reference sequences of MRS reference digital data (s0s1 . . . sMRS?1), MRS being less than M, and 2NRS being less than or equal to 2N. The method further includes making up each candidate sequence with remaining reference symbols to obtain at least one complete candidate sequence of M digital data, and determining the sequence of N bits ({circumflex over (x)}0{circumflex over (x)}1 . . . {circumflex over (x)}N?1) from the complete candidate sequences.

Abstract: Successive sequences of interleaved data samples extracted from a virtual memory having L0 columns and C0 rows are de-interleaved. The de-interleaving includes receiving each sequence of the interleaved data samples, and writing row by row the received sequences of interleaved data samples in a de-interleaving memory array having L rows and C columns, with L being greater or equal to L0 and C being greater or equal to C0. The data samples stored in the de-interleaving memory array are de-interleaved sub-array by sub-array. Each sub-array is a square cluster array having a number SQ of rows and columns. A cluster array is a row of the square cluster array comprising SQ data samples, with the number L of rows and the number C of columns of the de-interleaving memory array being multiples of the number SQ of rows and columns.

Abstract: A method for de-interleaving S2 received sequences of interleaved received data samples respectively issued from S2 physical channels and to be associated with S1 output transport channels is provided. The S2 received sequences have been delivered, before transmission by a two-stage multi-interleaving device, from S1 initial sequences of ordered data samples respectively associated to S1 initial transport channels. The two-stage multi-interleaving device includes a first stage including S1 interleaving blocks respectively associated to the S1 initial transport channels, a second stage including S2 interleaving blocks respectively associated to the S2 physical channels, and an inter-stage of predetermined data-routing functions connected between the first and second stages.