Abstract: A digital-to-analog conversion device that has one or more conversion cells, each cell coupled to a master voltage source and to a specific binary input element. The conversion cells include binary-weighted or binary-sized output transistors such that each output transistor, when called upon, delivers a unique analog output current corresponding to a particular binary signal. The master potential provided by a stable source is supplied to the control nodes of the output transistors so that the potential at those control nodes remains constant. Switching on and off of the output transistors is achieved by regulating the sources of those transistors rather than their gates. By regulating the operation of the output transistors at their sources, the present invention provides a digital-to-analog converter and a conversion method with little switching noise and minimal switching delay.

Abstract: A broadband low-gain system for automatically frequency-locking a signal where the system uses digital and analog devices and techniques. The system includes a comparator, an up/down counter, a digital-to-analog converter, a decoder, a ring oscillator and a downcounter. The digital control signal is provided by the decoder and actuates one of a plurality of ring oscillator stages. The analog control signal is provided by the digital-to analog-converter and controls a fine-tune mechanism in the actuated stage. The system includes a master reset for clearing the counters.

Abstract: An ECL to TTL translator circuit incorporates an ECL input gate, a TTL output gate, and a voltage amplifier transistor element circuit coupled between the ECL input gate and TTL output gate for effecting the translation. The ECL gate has differential ECL inputs for receiving ECL input signals at least at one of the ECL inputs (V.sub.IN) and differential first and second ECL output nodes (A, B). First and second emitter follower output circuits (Q7, Q3) are coupled to the respective first and second ECL output nodes (A, B). The TTL gate (12) has a TTL output (V.sub.OUT) for delivering TTL output signals corresponding to ECL input signals. The TTL gate phase splitter transistor element (Q9) controls the TTL output (V.sub.OUT). The collector node of a voltage amplifier transistor element (Q6) is coupled to a base node of the phase splitter transistor element (Q9) for controlling the conducting state of the phase splitter transistor element out of phase with the voltage amplifier transistor element.

Abstract: The lower output pulldown tristate circuit for a TTL tristate output buffer circuit includes the enable signal invertor buffer having an OE signal input and an OE signal output providing output enable OE signals, and a Miller killer transistor element having collector and emitter nodes coupled between the base node of the TTL tristate output pulldown transistor and the low potential power rail. The base node of an emitter follower transistor element is coupled to the OE signal input and the emitter node provides a DC Miller killer DCMK signal output in phase with the OE signal input. A voltage divider couples the DCMK signal output to the base node of the Miller killer transistor element for discharging the base of the output pulldown transistor in response ot a high potential DCMK signal during the high impedance tristate at the output. The DC Miller killer circuit is applied in a high speed TTL tristate output and multi-bit line driver.

Abstract: The output enable (OE) cutoff driver gate of a cutoff driver circuit is coupled to receive OE signals of high and low potential and hold an ECL logic gate in the cutoff state in response to one of the high and low OE signals. An OE signal driver circuit provides the OE signals of high and low potential to the OE cutoff driver gate. The OE cutoff driver current sink for sinking current from the OE cutoff driver gate is provided by a current switch circuit for switching sinking current on and off in response to current switch signals of high and low potential in phase with the OE signals. The current switch circuit switches on sinking current when the OE cutoff driver gate is holding the ECL logic gate in the cutoff state. The current switch circuit switches off sinking current for reducing power dissipation when the ECL logic gate is out of the cutoff state. The current switch circuit is provided by a current mirror circuit.

Abstract: An anti-simultaneous conduction transistor is incorporated into the standard TTL circuit totem pole to reduce simultaneous conduction of the pullup and pulldown transistor elements of the totem pole. The collector of the active discharge anti-simultaneous conduction transistor element (Q5) is operatively coupled to a base of the pullup transistor element (Q2,Q3) through a diode (D5), the emitter is coupled to low potential, and the base is coupled to the base of the pulldown transistor element (Q4) through ballast resistance (R6,R7). The anti-simultaneous conduction transistor element (Q5) mirrors the conducting state of the pulldown transistor element (Q4) without current hogging substantially diverting or discharging base current from the base of the pullup transistor element (Q2,Q3) whenever the pulldown transistor element (Q4) is conducting. Undesirable current spikes in the sourcing current are avoided by preventing simultaneous conduction in the totem pole.

Abstract: A transient voltage difference circuit is coupled into a TTL current sinking output circuit for transient performance enhancement during transition from high to low level potential at the output. The TTL output circuit includes a pulldown transistor element for sinking current from an output node to low potential, a base drive transistor for driving the base of a current sinking pulldown transistor element, an input base node of the base drive transistor coupled to receive input signals of high and low level potential, and a voltage clamp network coupled between the input base node and low potential for maintaining a potential level at the input base node sufficient to turn on the base drive transistor. An RC network is coupled between the input base node and low potential.

Abstract: A TTL to ECL/CML translator circuit delivers differential or complementary ECL logic output signals in response to TTL input signals with voltage gain, small output voltage swing and with a narrow transition region. The TTL input circuit is coupled to a current mirror circuit with first and second current mirror branch circuits. A differential amplifier gate circuit with differential amplifier first and second gate transistor elements co-acts with the current mirror circuit. The second current mirror branch circuit also constitutes the differential amplifier first gate transistor element. A threshold clamp circuit applies a threshold voltage level at the base node of the differential amplifier second gate transistor element thereby establishing a TTL input threshold at the threshold voltage level. First and second ECL output circuits are coupled to the collector nodes of the differential amplifier first and second gate transistor elements for delivering complementary ECL output signals.

Abstract: A pseudo-rail circuit is coupled between the differential output gate or buffer of an emitter coupled logic or current mode logic (ECL/CML) circuit and the high potential level power rail. The pseudo-rail circuit provides a pseudo-rail node. A first clamp circuit is coupled to the pseudo-rail node for clamping the pseudo-rail node at a first potential level in response to a first control signal. A second clamp circuit is coupled to the pseudo-rail node for clamping at a second potential level in response to a second control signal. A clamp switching circuit alternately applies the first and second clamp circuits to the pseudo-rail node in response to the control signals. As a cutoff driver circuit, the first clamp circuit of the pseudo-rail circuit applies the high potential level of the power rail to the pseudo-rail node. The second claim circuit pulls down the pseudo-rail node to hold the output of the differential output gate in the cutoff state.

Abstract: An emitter follower current switch circuit is provided for emitter coupled logic or current mode logic (ECL/CML) circuits having output buffer emitter follower transistor elements which source true and complementary output signals of high and low potential to respective true and complementary outputs of the ECL/CML gate. The emitter follower current switch circuit effectively disconnects the output current sink from and ECL/CML gate output and corresponding output buffer emitter follower transistor element when the corresponding output is at high potential. At each output a current switch transistor element is coupled between the respective output buffer emitter follower transistor element and the output current sink. A control circuit controls the conducting state of the current switch transistor element so that it is on (conducting) or off (non-conducting) for corresponding output signals of low and high potential respectively.