Abstract: A process for fabricating an RF type, MOSFET device, concentrating on reducing performance degrading gate resistance, has been developed. The process features formation of a stacked gate structure, comprised of a metal gate contact structure located directly overlying a portion of an underlying polysilicon gate structure, in a region in which the polysilicon gate structure is located on an active device region of a semiconductor substrate. Subsequent formation of an overlying metal interconnect structure, results in reduced gate resistance due to the direct vertical conductive path from the metal interconnect structure to the polysilicon gate structure, through the metal gate contact structure. A novel process sequence, requiring no photolithographic processing, is used to self-align the metal gate contact structure to the underlying polysilicon gate structure.