Patents by Inventor Jumpei Konno
Jumpei Konno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10199562Abstract: A method of fabricating an electronic device, the method including: arranging a device chip with no bump located on a lower surface of the device chip on a mounting substrate including a bump located on an upper surface of the mounting substrate; and bonding a pad located on the lower surface of the device chip and the bump by applying an ultrasonic wave to the device chip from an upper surface of the device chip.Type: GrantFiled: July 11, 2017Date of Patent: February 5, 2019Assignee: TAIYO YUDEN CO., LTD.Inventors: Shinji Yamamoto, Jumpei Konno, Takashi Miyagawa
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Publication number: 20180033952Abstract: A method of fabricating an electronic device, the method including: arranging a device chip with no bump located on a lower surface of the device chip on a mounting substrate including a bump located on an upper surface of the mounting substrate; and bonding a pad located on the lower surface of the device chip and the bump by applying an ultrasonic wave to the device chip from an upper surface of the device chip.Type: ApplicationFiled: July 11, 2017Publication date: February 1, 2018Applicant: TAIYO YUDEN CO., LTD.Inventors: Shinji YAMAMOTO, Jumpei KONNO, Takashi MIYAGAWA
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Patent number: 9818678Abstract: To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.Type: GrantFiled: March 23, 2014Date of Patent: November 14, 2017Assignee: Renesas Electronics CorporationInventors: Jumpei Konno, Takafumi Nishita, Nobuhiro Kinoshita, Kazunori Hasegawa, Michiaki Sugiyama
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Patent number: 9455240Abstract: Reliability of a semiconductor device is improved. Each of a plurality of terminals formed on a chip mounting surface included in a wiring substrate has a shape in which a narrow width portion is arranged between adjacent wide width portions in plan view. Moreover, a center of a tip end surface of each of a plurality of protruding electrodes formed on a semiconductor chip mounted on the wiring substrate is arranged at a position where it overlaps the narrow width portion in plan view, and the plurality of terminals and the plurality of protruding electrodes are electrically connected to each other via a solder member.Type: GrantFiled: December 23, 2013Date of Patent: September 27, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Jumpei Konno, Takafumi Nishita, Nobuhiro Kinoshita, Kazunori Hasegawa, Michiaki Sugiyama
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Patent number: 9349678Abstract: The reliability of a semiconductor device is improved. A probe mark is formed on a probe region of a pad covered with a protective insulating film. And, a pillar-shaped electrode has a first portion formed on an opening region and a second portion that is extended over the probe region from the upper portion of the opening region. At this time, a center position of the opening region is shifted from a center position of the pillar-shaped electrode that is opposed to a bonding finger.Type: GrantFiled: June 25, 2015Date of Patent: May 24, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yoshihiro Ono, Nobuhiro Kinoshita, Tsuyoshi Kida, Jumpei Konno, Kenji Sakata, Kentaro Mori, Shinji Baba
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Publication number: 20150380345Abstract: The reliability of a semiconductor device is improved. A probe mark is formed on a probe region of a pad covered with a protective insulating film. And, a pillar-shaped electrode has a first portion formed on an opening region and a second portion that is extended over the probe region from the upper portion of the opening region. At this time, a center position of the opening region is shifted from a center position of the pillar-shaped electrode that is opposed to a bonding finger.Type: ApplicationFiled: June 25, 2015Publication date: December 31, 2015Inventors: Yoshihiro ONO, Nobuhiro KINOSHITA, Tsuyoshi KIDA, Jumpei KONNO, Kenji SAKATA, Kentaro MORI, Shinji BABA
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Publication number: 20150236003Abstract: A method of manufacturing a semiconductor device obtained by laminating a first semiconductor chip and a second semiconductor chip with different planar sizes when seen in a plan view on a wiring board via an adhesive material, in which the second semiconductor chip with a relatively larger planar size is mounted on the first semiconductor chip with a relatively smaller planar size. Also, after the first and second semiconductor chips are mounted, the first and second semiconductor chips are sealed with resin. Here, before sealing with the resin, a gap between the second semiconductor chip and the wiring board is previously sealed with the adhesive material used when the first and second semiconductor chips are mounted.Type: ApplicationFiled: September 14, 2012Publication date: August 20, 2015Applicant: Renesas Electronics CorporationInventors: Jumpei Konno, Takafumi Nishita, Kenji Sakata, Nobuhiro Kinoshita, Michiaki Sugiyama, Tsuyoshi Kida, Yoshihiro Ono
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Publication number: 20140312498Abstract: To provide a semiconductor device having improved reliability. In a wiring board of BGA, an insulation layer has thereon a plurality of bonding leads. The insulation layer is comprised of a prepreg having a glass cloth and a resin layer not having the glass cloth. The prepreg has thereon the resin layer. The bonding leads are arranged directly on the soft resin layer and are therefore supported by this soft resin layer. When a load is applied to each of the bonding leads during flip chip bonding, the resin layer sinks, by which a stress applied to a semiconductor chip can be relaxed.Type: ApplicationFiled: March 30, 2014Publication date: October 23, 2014Applicant: Renesas Electronics CorporationInventors: Michiaki Sugiyama, Jumpei Konno
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Publication number: 20140203431Abstract: To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.Type: ApplicationFiled: March 23, 2014Publication date: July 24, 2014Applicant: Renesas Electronics CorporationInventors: Jumpei KONNO, Takafumi NISHITA, Nobuhiro KINOSHITA, Kazunori HASEGAWA, Michiaki SUGIYAMA
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Publication number: 20140183759Abstract: Reliability of a semiconductor device is improved. Each of a plurality of terminals formed on a chip mounting surface included in a wiring substrate has a shape in which a narrow width portion is arranged between adjacent wide width portions in plan view. Moreover, a center of a tip end surface of each of a plurality of protruding electrodes formed on a semiconductor chip mounted on the wiring substrate is arranged at a position where it overlaps the narrow width portion in plan view, and the plurality of terminals and the plurality of protruding electrodes are electrically connected to each other via a solder member.Type: ApplicationFiled: December 23, 2013Publication date: July 3, 2014Applicant: Renesas Electronics CorporationInventors: Jumpei Konno, Takafumi Nishita, Nobuhiro Kinoshita, Kazunori Hasegawa, Michiaki Sugiyama
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Patent number: 8701972Abstract: To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.Type: GrantFiled: August 29, 2013Date of Patent: April 22, 2014Assignee: Renesas Electronics CorporationInventors: Takafumi Nishita, Nobuhiro Kinoshita, Jumpei Konno, Michiaki Sugiyama, Kazunori Hasegawa
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Patent number: 8633103Abstract: In order to achieve the highly reliable and highly functional semiconductor device capable of the high-speed transmission by stacking thin chips and substrates, a connecting process and a connecting structure capable of making a solid connection at a low temperature with a low load and maintaining the shape of a connecting portion even if the connecting portion is heated in the stacking process and the subsequent mounting process are provided. In a semiconductor device in which semiconductor chips or wiring boards on which semiconductor chips are mounted are stacked, a connecting structure between electrodes of the stacked semiconductor chips or wiring boards includes a pair of electrodes mainly made of Cu and a solder layer made of Sn—In based alloy sandwiched between the electrodes, and Sn—Cu—Ni intermetallic compounds are dispersed in the solder layer.Type: GrantFiled: June 13, 2010Date of Patent: January 21, 2014Assignee: Renesas Electronics CorporationInventors: Hanae Hata, Masato Nakamura, Nobuhiro Kinoshita, Jumpei Konno, Chiko Yorita
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Publication number: 20140004661Abstract: To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.Type: ApplicationFiled: August 29, 2013Publication date: January 2, 2014Applicant: Renesas Electronics CorporationInventors: Jumpei KONNO, Takafumi NISHITA, Nobuhiro KINOSHITA, Kazunori HASEGAWA, Michiaki SUGIYAMA
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Patent number: 8534532Abstract: To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.Type: GrantFiled: June 24, 2012Date of Patent: September 17, 2013Assignee: Renesas Electronics CorporationInventors: Jumpei Konno, Takafumi Nishita, Nobuhiro Kinoshita, Kazunori Hasegawa, Michiaki Sugiyama
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Publication number: 20130001274Abstract: To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.Type: ApplicationFiled: June 24, 2012Publication date: January 3, 2013Inventors: Jumpei KONNO, Takafumi Nishita, Nobuhiro Kinoshita, Kazunori Hasegawa, Michiaki Sugiyama
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Publication number: 20110012263Abstract: In order to achieve the highly reliable and highly functional semiconductor device capable of the high-speed transmission by stacking thin chips and substrates, a connecting process and a connecting structure capable of making a solid connection at a low temperature with a low load and maintaining the shape of a connecting portion even if the connecting portion is heated in the stacking process and the subsequent mounting process are provided. In a semiconductor device in which semiconductor chips or wiring boards on which semiconductor chips are mounted are stacked, a connecting structure between electrodes of the stacked semiconductor chips or wiring boards includes a pair of electrodes mainly made of Cu and a solder layer made of Sn—In based alloy sandwiched between the electrodes, and Sn—Cu—Ni intermetallic compounds are dispersed in the solder layer.Type: ApplicationFiled: June 13, 2010Publication date: January 20, 2011Inventors: Hanae HATA, Masato Nakamura, Nobuhiro Kinoshita, Jumpei Konno, Chiko Yorita
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Patent number: 7598121Abstract: A method of manufacturing a semiconductor device includes the steps of: grinding the rear surface of a semiconductor wafer to reduce its thickness; flattening the rear surface of the semiconductor wafer; dividing the semiconductor wafer into a plurality of semiconductor chips; forming gold bumps on the electrodes of the plurality of semiconductor chips; applying NCP to the front surface of a packaging board; and arranging the semiconductor chips over the packaging board through the NCP and pressing the back surfaces of the semiconductor chips to flip-chip bond the semiconductor chips to the packaging board. Therefore, it is possible to prevent NCP from rising onto the back surfaces of the semiconductor chips at the time of flip-chip bonding, whereby separation and cracking caused by a high-temperature treatment for assembly and mounting of a semiconductor device can be prevented and the reliability of the semiconductor device can be improved.Type: GrantFiled: January 3, 2007Date of Patent: October 6, 2009Assignee: Renesas Technology Corp.Inventors: Nobuhiro Kinoshita, Jumpei Konno
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Publication number: 20070111384Abstract: A method of manufacturing a semiconductor device includes the steps of: grinding the rear surface of a semiconductor wafer to reduce its thickness; flattening the rear surface of the semiconductor wafer; dividing the semiconductor wafer into a plurality of semiconductor chips; forming gold bumps on the electrodes of the plurality of semiconductor chips; applying NCP to the front surface of a packaging board; and arranging the semiconductor chips over the packaging board through the NCP and pressing the back surfaces of the semiconductor chips to flip-chip bond the semiconductor chips to the packaging board. Therefore, it is possible to prevent NCP from rising onto the back surfaces of the semiconductor chips at the time of flip-chip bonding, whereby separation and cracking caused by a high-temperature treatment for assembly and mounting of a semiconductor device can be prevented and the reliability of the semiconductor device can be improved.Type: ApplicationFiled: January 3, 2007Publication date: May 17, 2007Inventors: Nobuhiro Kinoshita, Jumpei Konno
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Publication number: 20050140023Abstract: A method of manufacturing a semiconductor device, includes the steps of: grinding the rear surface of a semiconductor wafer to reduce its thickness; flattening the rear surface of the semiconductor wafer; dividing the semiconductor wafer into a plurality of semiconductor chips; forming gold bumps on the electrodes of the plurality of semiconductor chips; applying NCP to the front surface of a packaging board; and arranging the semiconductor chips over the packaging board through the NCP and pressing the back surfaces of the semiconductor chips to flip-chip bond the semiconductor chips to the packaging board. Therefore, it is possible to prevent NCP from rising onto the back surfaces of the semiconductor chips at the time of flip-chip bonding, whereby separation and cracking caused by a high-temperature treatment for assembly and mounting of a semiconductor device can be prevented and the reliability of the semiconductor device can be improved.Type: ApplicationFiled: December 21, 2004Publication date: June 30, 2005Inventors: Nobuhiro Kinoshita, Jumpei Konno