Patents by Inventor Jum Yong Park
Jum Yong Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240014177Abstract: A semiconductor package includes a redistribution substrate. A first semiconductor chip is disposed on the redistribution substrate. The first semiconductor chip includes a first semiconductor substrate, first through vias penetrating through the first semiconductor substrate, and a first bonding layer disposed on the first semiconductor substrate. The first bonding layer is electrically connected to the first through vias. A second semiconductor chip includes a second semiconductor substrate and a second bonding layer disposed on the second semiconductor substrate. The second bonding layer is bonded to the first bonding layer. A filling insulating film is disposed on the redistribution substrate. The filling insulating film covers the first semiconductor chip and the second semiconductor chip. An upper surface of the filling insulating film is disposed on a level above an upper surface of the first semiconductor chip and an upper surface of the second semiconductor chip.Type: ApplicationFiled: July 3, 2023Publication date: January 11, 2024Inventors: Young Kun JEE, Un-Byoung KANG, Jum Yong PARK, Jong-Hyeon CHANG
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Patent number: 11798906Abstract: A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.Type: GrantFiled: December 15, 2021Date of Patent: October 24, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jeong-gi Jin, Nae-in Lee, Jum-yong Park, Jin-ho Chun, Seong-min Son, Ho-Jin Lee
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Publication number: 20230021152Abstract: A semiconductor device includes an insulating layer on a substrate; a via extending from within the substrate and extending through one face of the substrate and a bottom face of a trench defined in the insulating layer such that a portion of a sidewall and a top face of the via are exposed through the substrate; and a pad contacting the exposed portion of the sidewall and the top face of the via. The pad fills the trench. The insulating layer includes a passivation layer on the substrate, and a protective layer is on the passivation layer. An etch stop layer is absent between the passivation layer and the protective layer. A vertical level of a bottom face of the trench is higher than a vertical level of one face of the substrate and is lower than a vertical level of a top face of the passivation layer.Type: ApplicationFiled: February 7, 2022Publication date: January 19, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: Hyun Su HWANG, Jun Yun KWEON, Jum Yong PARK, Sol Ji SONG, Dong Joon OH, Chung Sun LEE
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Publication number: 20220108962Abstract: A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.Type: ApplicationFiled: December 15, 2021Publication date: April 7, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Jeong-gi JIN, Nae-in LEE, Jum-yong PARK, Jin-ho CHUN, Seong-min SON, Ho-Jin LEE
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Patent number: 11251144Abstract: A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.Type: GrantFiled: October 30, 2019Date of Patent: February 15, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Jeong-gi Jin, Nae-in Lee, Jum-yong Park, Jin-ho Chun, Seong-min Son, Ho-jin Lee
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Publication number: 20200066666Abstract: A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.Type: ApplicationFiled: October 30, 2019Publication date: February 27, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Jeong-gi Jin, Nae-in Lee, Jum-yong Park, Jin-ho Chun, Seong-min Son, Ho-jin Lee
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Patent number: 10483224Abstract: A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.Type: GrantFiled: October 24, 2017Date of Patent: November 19, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Jeong-gi Jin, Nae-in Lee, Jum-yong Park, Jin-ho Chun, Seong-min Son, Ho-jin Lee
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Publication number: 20180138137Abstract: A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.Type: ApplicationFiled: October 24, 2017Publication date: May 17, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Jeong-gi JIN, Nae-in Lee, Jum-yong Park, Jin-ho Chun, Seong-min Son, Ho-jin Lee
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Patent number: 9865581Abstract: A first insulating layer is formed on a substrate. An opening is formed in the first insulating layer. A barrier layer is formed on the first insulating layer and conforming to sidewalls of the first insulating layer in the opening, and a conductive layer is formed on the barrier layer. Chemical mechanical polishing is performed to expose the first insulating layer and leave a barrier layer pattern in the opening and a conductive layer pattern on the barrier layer pattern in the opening, wherein a portion of the conductive layer pattern protrudes above an upper surface of the insulating layer and an upper surface of the barrier layer pattern. A second insulating layer is formed on the first insulating layer, the barrier layer pattern and the conductive layer pattern and planarized to expose the conductive layer pattern. A second substrate may be bonded to the exposed conductive layer pattern.Type: GrantFiled: November 13, 2015Date of Patent: January 9, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Joo-Hee Jang, Pil-Kyu Kang, Seok-Ho Kim, Tae-Yeong Kim, Hyo-Ju Kim, Byung-Lyul Park, Jum-Yong Park, Jin-Ho An, Kyu-Ha Lee, Yi-Koan Hong
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Patent number: 9691685Abstract: A semiconductor device includes a substrate having a die region and a scribe region surrounding the die region, a plurality of via structures penetrating through the substrate in the die region, a portion of the via structure being exposed over a surface of the substrate, and a protection layer pattern structure provided on the surface of the substrate surrounding a sidewall of the exposed portion of the via structure and having a protruding portion covering at least a portion of the scribe region adjacent to the via structure.Type: GrantFiled: May 25, 2016Date of Patent: June 27, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyu-Ha Lee, Hyung-Jun Jeon, Jum-Yong Park, Byung-Lyul Park, Ji-Soon Park, Jin-Ho An, Jin-Ho Chun
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Publication number: 20170033032Abstract: A semiconductor device includes a substrate having a die region and a scribe region surrounding the die region, a plurality of via structures penetrating through the substrate in the die region, a portion of the via structure being exposed over a surface of the substrate, and a protection layer pattern structure provided on the surface of the substrate surrounding a sidewall of the exposed portion of the via structure and having a protruding portion covering at least a portion of the scribe region adjacent to the via structure.Type: ApplicationFiled: May 25, 2016Publication date: February 2, 2017Inventors: Kyu-Ha Lee, Hyung-Jun Jeon, Jum-Yong Park, Byung-Lyul Park, Ji-Soon Park, Jin-Ho An, Jin-Ho Chun
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Publication number: 20160141282Abstract: A first insulating layer is formed on a substrate. An opening is formed in the first insulating layer. A barrier layer is formed on the first insulating layer and conforming to sidewalls of the first insulating layer in the opening, and a conductive layer is formed on the barrier layer. Chemical mechanical polishing is performed to expose the first insulating layer and leave a barrier layer pattern in the opening and a conductive layer pattern on the barrier layer pattern in the opening, wherein a portion of the conductive layer pattern protrudes above an upper surface of the insulating layer and an upper surface of the barrier layer pattern. A second insulating layer is formed on the first insulating layer, the barrier layer pattern and the conductive layer pattern and planarized to expose the conductive layer pattern. A second substrate may be bonded to the exposed conductive layer pattern.Type: ApplicationFiled: November 13, 2015Publication date: May 19, 2016Inventors: Joo-Hee Jang, Pil-Kyu Kang, Seok-Ho Kim, Tae-Yeong Kim, Hyo-Ju Kim, Byung-Lyul Park, Jum-Yong Park, Jin-Ho An, Kyu-Ha Lee, Yi-Koan Hong
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Patent number: 9159732Abstract: A method for fabricating a semiconductor device includes forming landing plugs over a substrate, forming a trench by etching the substrate between the landing plugs, forming a buried gate to partially fill the trench, forming a gap-fill layer to gap-fill an upper side of the buried gate, forming protruding portions of the landing plugs, and trimming the protruding portions of the landing plugs.Type: GrantFiled: July 19, 2012Date of Patent: October 13, 2015Assignee: Hynix Semiconductor Inc.Inventors: Jong-Han Shin, Jum-Yong Park
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Publication number: 20140199810Abstract: A fabricating method for a semiconductor device is provided. The fabricating method includes providing a first wafer, forming a sacrificial layer on the first wafer, forming a release layer on the sacrificial layer, forming an adhesive layer on the release layer, and placing a second wafer on the adhesive layer and bonding the first wafer to the second wafer.Type: ApplicationFiled: January 13, 2014Publication date: July 17, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Jin-Ho Park, Pil-Kyu Kang, Tae-Yeong Kim, Byung-Lyul Park, Jum-Yong Park, Kyu-Ha Lee, Deok-Young Jung, Gil-Heyun Choi
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Patent number: 8753966Abstract: A method for fabricating a semiconductor device is provided, the method includes forming a plug conductive layer over an entire surface of a substrate, etching the plug conductive layer to form landing plugs, etching the substrate between the landing plugs to form a trench, forming a gate insulation layer over a surface of the trench and forming a buried gate partially filling the trench over the gate insulation layer.Type: GrantFiled: January 18, 2013Date of Patent: June 17, 2014Assignee: SK Hynix Inc.Inventors: Jum-Yong Park, Jong-Han Shin
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Patent number: 8384135Abstract: A phase-change random access memory device includes a semiconductor substrate, a bottom electrode structure formed on the semiconductor substrate, a cylindrical bottom electrode contact that includes a conductive material layer, which is in contact with the bottom electrode, and a cylindrical phase-change material layer that is in contact with the bottom electrode contact. Therefore, the contact area between the bottom electrode contact and the phase-change material layer can be minimized.Type: GrantFiled: June 20, 2011Date of Patent: February 26, 2013Assignee: SK hynix Inc.Inventors: Cheol Hwi Ryu, Hyung Soon Park, Jong Han Shin, Jum Yong Park, Sung Jun Kim
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Patent number: 8357600Abstract: A method for fabricating a semiconductor device is provided, the method includes forming a plug conductive layer over an entire surface of a substrate, etching the plug conductive layer to form landing plugs, etching the substrate between the landing plugs to form a trench, forming a gate insulation layer over a surface of the trench and forming a buried gate partially filling the trench over the gate insulation layer.Type: GrantFiled: November 6, 2009Date of Patent: January 22, 2013Assignee: Hynix Semiconductor Inc.Inventors: Jong-Han Shin, Jum-Yong Park
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Patent number: 8314030Abstract: A method for fabricating a semiconductor device through a chemical mechanical polishing (CMP) process is provided. The CMP process is performed by using a slurry. The semiconductor device fabrication method can ensure the reliability and economical efficiency of the device by performing a CMP process using a CMP slurry having a high polishing selectivity with respect to a target surface, an anti-scratch characteristic, and a high global planarization characteristic.Type: GrantFiled: June 23, 2009Date of Patent: November 20, 2012Assignee: Hynix Semiconductor, Inc.Inventors: Jum-Yong Park, Noh-Jung Kwak, Yong-Soo Choi, Cheol-Hwi Ryu
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Publication number: 20120280313Abstract: A method for fabricating a semiconductor device includes forming landing plugs over a substrate, forming a trench by etching the substrate between the landing plugs, forming a buried gate to partially fill the trench, forming a gap-fill layer to gap-fill an upper side of the buried gate, forming protruding portions of the landing plugs, and trimming the protruding portions of the landing plugs.Type: ApplicationFiled: July 19, 2012Publication date: November 8, 2012Inventors: Jong-Han SHIN, Jum-Yong PARK
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Patent number: 8247324Abstract: A method for fabricating a semiconductor device includes forming landing plugs over a substrate, forming a trench by etching the substrate between the landing plugs, forming a buried gate to partially fill the trench, forming a gap-fill layer to gap-fill an upper side of the buried gate, forming protruding portions of the landing plugs, and trimming the protruding portions of the landing plugs.Type: GrantFiled: June 30, 2010Date of Patent: August 21, 2012Assignee: Hynix Semiconductor Inc.Inventors: Jong-Han Shin, Jum-Yong Park