Abstract: A tissue restoration composition in a colloidal phase, includes a copolymer in which a hydrophobic biocompatible polymer and a hydrophilic biocompatible polymer are polymerized and which is dispersed in water. The colloidal phase has increased viscosity by heating the copolymer dispersed in water. The colloidal phase has a viscosity, by the heating, of 20-200,000 cP.

Abstract: A semiconductor package and method of manufacturing the same are provided. The semiconductor package includes a first semiconductor chip having a first connection pad disposed on a first surface, and a second surface opposite to the first surface, a second semiconductor chip on the second surface and having a second connection pad disposed on a third surface, and a fourth surface opposite to the third surface, a connection structure on the first surface, including a redistribution layer connected to the first and second connection pads, a fifth surface facing the first surface, a sixth surface opposite to the fifth surface, and a grounding pad, a first connecting wire connecting the first connection pad and the redistribution layer, a second connecting wire connecting the second connection pad and the redistribution layer, a shielding plate on the fourth surface, and a shielding wire connecting the shielding plate and the grounding pad.

Abstract: A tissue restoration composition in a colloidal phase, includes a copolymer in which a hydrophobic biocompatible polymer and a hydrophilic biocompatible polymer are polymerized and which is dispersed in water. The colloidal phase has increased viscosity by heating the copolymer dispersed in water. The colloidal phase has a viscosity, by the heating, of 20-200,000 cP.

Abstract: Provided is a tooth analysis server including: a server communication unit linked with a tooth photographing device for photographing teeth to communicate with a user terminal; a database management unit for managing an image of the photographed teeth as data; an analysis unit for analyzing a state of the teeth of the user according to the request; and a result providing unit for providing an analysis result for the state of the teeth of the user to the user terminal, wherein the analysis unit receives a first image obtained by photographing the teeth of the user at a first speed from the tooth photographing device to perform a first analysis, and receives a second image obtained by photographing the doubtful area at a second speed slower than the first speed from the tooth photographing device to perform a second analysis.

Abstract: The present invention relates to porous microparticles of a biodegradable polymer, and a polymer filler comprising the same.

Abstract: The present invention relates to porous microparticles of a biodegradable polymer, and a polymer filler comprising the same.

Abstract: Disclosed are a composition for tissue repair treatment using a non-toxic biocompatible polymer and a method for manufacturing the same. The composition includes a copolymer in which a hydrophobic biocompatible polymer and a hydrophilic biocompatible polymer are polymerized, and having a colloidal phase in which the copolymer is dispersed in water. The method including: preparing a polymer by polymerizing a hydrophobic biocompatible polymer and a hydrophilic biocompatible polymer; and obtaining a colloidal solution by adding the polymer to water.

Abstract: Provided is a non-woven fabric type composite hemostatic agent, obtained by overlapping (i) at least one web of a first polymer selected from the group consisting of biodegradable polymers, oxidative regeneration cellulose, and alkali metal salt neutralizers of oxidative regeneration cellulose and (ii) at least one web of a second polymer selected from the group consisting of oxidative regeneration cellulose and alkali metal salt neutralizers thereof, followed by needle punching, compressing, and integrating.

Abstract: A compensation circuit for use with an input buffer includes an input buffer configured to amplify an input signal and output a compensated signal. A process detector includes a replica of the input buffer. The process detector is configured to output at least one comparison signal indicating a variation in the input buffer. The input buffer controls an output signal based on the at least one comparison signal.

Abstract: A compensation circuit for use with an input buffer includes an input buffer configured to amplify an input signal and output a compensated signal. A process detector includes a replica of the input buffer. The process detector is configured to output at least one comparison signal indicating a variation in the input buffer. The input buffer controls an output signal based on the at least one comparison signal.

Abstract: A delay locked loop (DLL) circuit is disclosed. The DLL circuit includes a delay circuit and a phase adjusting circuit. The phase adjusting circuit is configured to receive a clock signal output from the delay circuit, pass the clock signal through a N-divider and a replica path to create a N-divided delay signal, and detect phase information about an external clock signal in response to a rising edge and a falling edge of the N-divided delay signal, wherein N denotes a natural number. The delay circuit is configured to output the clock signal by adjusting a phase of the external clock signal in response to a result of the detection. A semiconductor device, semiconductor system, and method are also disclosed.

Abstract: A delay-locked loop includes a delay line and a duty correction block. The delay line includes receives an input clock signal and includes a cascade of delay cells for respectively generating a plurality of delayed input clock signals based on the input clock signal. The duty correction block is for correcting a duty ratio of the input clock signal based on a duty ratio of at least one clock signal from among the input clock signal and the plurality of delayed input clock signals in a first duty correction operation in which the duty ratio of the input clock signal is corrected, and correcting a duty ratio of an output clock signal based on the duty ratio of the output clock in a second duty correction operation in which the duty ratio of the output clock signal is corrected.

Abstract: A delay locked loop (DLL) circuit is disclosed. The DLL circuit includes a delay circuit and a phase adjusting circuit. The phase adjusting circuit is configured to receive a clock signal output from the delay circuit, pass the clock signal through a N-divider and a replica path to create a N-divided delay signal, and detect phase information about an external clock signal in response to a rising edge and a falling edge of the N-divided delay signal, wherein N denotes a natural number. The delay circuit is configured to output the clock signal by adjusting a phase of the external clock signal in response to a result of the detection. A semiconductor device, semiconductor system, and method are also disclosed.

Abstract: According to one embodiment, a method of performing fast locking in a delay locked loop circuit is disclosed. The method includes performing a first comparison comparing an input clock signal to a first feedback clock signal that is a non-inverted feedback clock signal, and performing a second comparison comparing the input clock signal to a second feedback clock signal that is the feedback clock signal inverted. The method also includes, based on the first and second comparisons, selecting one of the non-inverted feedback clock signal or the inverted feedback clock signal to synchronize with the input clock signal. In addition, the method includes synchronizing the selected clock signal with the input clock signal.

Abstract: A delay-locked loop includes a delay line and a duty correction block. The delay line includes receives an input clock signal and includes a cascade of delay cells for respectively generating a plurality of delayed input clock signals based on the input clock signal. The duty correction block is for correcting a duty ratio of the input clock signal based on a duty ratio of at least one clock signal from among the input clock signal and the plurality of delayed input clock signals in a first duty correction operation in which the duty ratio of the input clock signal is corrected, and correcting a duty ratio of an output clock signal based on the duty ratio of the output clock in a second duty correction operation in which the duty ratio of the output clock signal is corrected.

Abstract: According to one embodiment, a method of performing fast locking in a delay locked loop circuit is disclosed. The method includes performing a first comparison comparing an input clock signal to a first feedback clock signal that is a non-inverted feedback clock signal, and performing a second comparison comparing the input clock signal to a second feedback clock signal that is the feedback clock signal inverted. The method also includes, based on the first and second comparisons, selecting one of the non-inverted feedback clock signal or the inverted feedback clock signal to synchronize with the input clock signal. In addition, the method includes synchronizing the selected clock signal with the input clock signal.

Abstract: Disclosed is a data output driver which improves the timing margin of a memory operation by reducing skew related to data output in a semiconductor memory device. A register receives and stores a plurality of first parallel data in synchronization with clock signal and outputs a plurality of second parallel data. A controller compares a plurality of parallel data currently inputted to register with a plurality of parallel data previously inputted to register in response to delayed clock signal, and calculates the number of data transitions based on the comparison result, and generates a control signal according to calculated number of data transitions. A clock signal delay part delays clock signal according to a logic level of control signal in order to generate a pair of corrected clock signals. A data selecting part selectively outputs odd or even numbered data among the plurality of second parallel data. An output driving part buffers and outputs output data of the data selecting part.

Abstract: Disclosed is a data output driver which improves the timing margin of a memory operation by reducing skew related to data output in a semiconductor memory device. A register receives and stores a plurality of first parallel data in synchronization with clock signal and outputs a plurality of second parallel data. A controller compares a plurality of parallel data currently inputted to register with a plurality of parallel data previously inputted to register in response to delayed clock signal, and calculates the number of data transitions based on the comparison result, and generates a control signal according to calculated number of data transitions. A clock signal delay part delays clock signal according to a logic level of control signal in order to generate a pair of corrected clock signals. A data selecting part selectively outputs odd or even numbered data among the plurality of second parallel data. An output driving part buffers and outputs output data of the data selecting part.

Abstract: A hula hoop, comprising of a plurality of arcuate modules individually having bulged portions with a connection plug and a connection socket being formed at opposite ends of each module, is disclosed. An annular groove is formed at the tip of each bulged portion, with a raised disc-shaped flat base having a continuous tang along its circular top edge and being defined by the annular groove. A recessed locking groove is formed along the root of the base. A pressure projection and a guide projection are interiorly formed on the socket. An engaging slot is formed on the plug at a position diametrically opposite to the guide groove. An engaging projection is formed on the socket at a position corresponding to the engaging slot. A pressure dome, individually having a fitting ring, is attached to each bulged portion of the module. The lower edge of the pressure dome is seated in the annular groove with the fitting ring engaging with the tang of the base.