Abstract: A charge pump circuit in a DLL device used as a clock compensation device is disclosed. A controller for controlling current value and a driver for driving the controller are added to the existing charge pump circuit. Thus, the charge pump circuit reduces lock time and the size of output jitter so that performance of the DLL device can be improved.

Abstract: A delay locked loop circuit, comprising: first delay means for receiving an external clock signal to generate a delay clock signal; first oscillation means for generating a first pulse signal; second oscillation means for generating a second pulse signal; phase detection means for receiving the external clock signal and an internal clock signal and generating a phase detection signal; second delay means for delaying the delay clock signal by one period of the first pulse signal of the first oscillation means to generate a first plurality of clock signals; third delay means for delaying the delay clock signal by one period of the second pulse signal of the second oscillation means to generate a second plurality of clock signals; selection means for selecting a pair of clock signals having the same delay time from the first plurality of clock signals and the second plurality of clock signals; logic means for combining the pair of clock signals selected from the selection means to generate the internal clock sig

Abstract: A clock phase correction circuit for a semiconductor memory device reduces all lock ranges by using a half-mixer to a conventional delay locked loop (DLL) circuit, and thus generates a clock signal having a fast lock time and a very small jitter. In order to achieve this objective, a track portion having a plurality of phase converters and one half-mixer is provided between an input terminal of external clock and an input terminal of a delay means of the conventional DLL circuit, and approaches the phase of the external clock to a phase of the feedback clock. A phase difference between the corrected signal and the feedback clock is then reduced by the conventional DLL circuit. As a result, lock time becomes shorter, and the magnitude of a jitter becomes reduced.