Abstract: Active regions defined by device isolation layer are provided on a substrate. A word line crossing the active regions and a gate dielectric layer between the word line and the active regions are provided. A capping insulating pattern covering an upper surface of the word line and a bit line on the word line are provided. The word line may include a first conductive pattern and a second conductive pattern on the first conductive pattern. The first conductive pattern may include a first metal element. The second conductive pattern may include the first metal element, a work function adjustment element, and a diffusion barrier element. An atomic radius of the diffusion barrier element may be smaller than an atomic radius of the first metal element.

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device may include a substrate having a groove therein extending in a first direction, a gate insulating layer in the groove, a first conductive pattern in the groove and on the gate insulating layer, and a word line capping pattern in the groove and on the first conductive pattern. The first conductive pattern may include a first material and may include a first conductive portion adjacent to the word line capping pattern and a second conductive portion adjacent to a bottom end of the groove. A largest dimension of a grain of the first material of the first conductive portion may be equal to or larger than that of the first material of the second conductive portion.

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device may include a substrate having a groove therein extending in a first direction, a gate insulating layer in the groove, a first conductive pattern in the groove and on the gate insulating layer, and a word line capping pattern in the groove and on the first conductive pattern. The first conductive pattern may include a first material and may include a first conductive portion adjacent to the word line capping pattern and a second conductive portion adjacent to a bottom end of the groove. A largest dimension of a grain of the first material of the first conductive portion may be equal to or larger than that of the first material of the second conductive portion.

Abstract: Active regions defined by device isolation layer are provided on a substrate. A word line crossing the active regions and a gate dielectric layer between the word line and the active regions are provided. A capping insulating pattern covering an upper surface of the word line and a bit line on the word line are provided. The word line may include a first conductive pattern and a second conductive pattern on the first conductive pattern. The first conductive pattern may include a first metal element. The second conductive pattern may include the first metal element, a work function adjustment element, and a diffusion barrier element. An atomic radius of the diffusion barrier element may be smaller than an atomic radius of the first metal element.

Abstract: A semiconductor memory device is provided. The semiconductor device may include a semiconductor substrate having a device isolation trench defining active regions, a device isolation layer disposed in the device isolation trench, gate trenches extending in a first direction and crossing the active regions of the semiconductor substrate and the device isolation layer, word lines disposed in the gate trenches, respectively, each of the gate trenches may include first trench sections in the active regions and second trench sections in the device isolation layer, the first trench sections may have a first depth, and the second trench section may have a second depth greater than the first depth, the device isolation layer may include a lower portion positioned at a level lower than bottom surfaces of the first trench sections and an upper portion on the lower portion, and the lower portion may be formed of a dielectric material having a lower dielectric constant than that of the upper portion.

Abstract: Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device may include a substrate having a groove therein extending in a first direction, a gate insulating layer in the groove, a first conductive pattern in the groove and on the gate insulating layer, and a word line capping pattern in the groove and on the first conductive pattern. The first conductive pattern may include a first material and may include a first conductive portion adjacent to the word line capping pattern and a second conductive portion adjacent to a bottom end of the groove. A largest dimension of a grain of the first material of the first conductive portion may be equal to or larger than that of the first material of the second conductive portion.

Abstract: A semiconductor device may include a semiconductor substrate including an active region defined by a trench, a device isolation layer provided in the trench to surround the active region, a gate electrode extending in a direction crossing the active region, and formed on the active region and the device isolation layer, and a gate insulating layer between the active region and the gate electrode. The active region may have a first conductivity type, and the device isolation layer may include a first silicon oxide layer on an inner surface of the first trench and a different layer, selected from one of first metal oxide layer and a negatively-charged layer, on the first silicon oxide layer.

Abstract: A semiconductor device may include a semiconductor substrate including an active region defined by a trench, a device isolation layer provided in the trench to surround the active region, a gate electrode extending in a direction crossing the active region, and formed on the active region and the device isolation layer, and a gate insulating layer between the active region and the gate electrode. The active region may have a first conductivity type, and the device isolation layer may include a first silicon oxide layer on an inner surface of the first trench and a different layer, selected from one of first metal oxide layer and a negatively-charged layer, on the first silicon oxide layer.

Abstract: A semiconductor device may include a semiconductor substrate including an active region defined by a trench, a device isolation layer provided in the trench to surround the active region, a gate electrode extending in a direction crossing the active region, and formed on the active region and the device isolation layer, and a gate insulating layer between the active region and the gate electrode. The active region may have a first conductivity type, and the device isolation layer may include a first silicon oxide layer on an inner surface of the first trench and a different layer, selected from one of first metal oxide layer and a negatively-charged layer, on the first silicon oxide layer.

Abstract: A semiconductor device may include a semiconductor substrate including an active region defined by a trench, a device isolation layer provided in the trench to surround the active region, a gate electrode extending in a direction crossing the active region, and formed on the active region and the device isolation layer, and a gate insulating layer between the active region and the gate electrode. The active region may have a first conductivity type, and the device isolation layer may include a first silicon oxide layer on an inner surface of the first trench and a different layer, selected from one of first metal oxide layer and a negatively-charged layer, on the first silicon oxide layer.

Abstract: A method of fabricating a semiconductor device, can be provided by forming gate structures for transistors on a semiconductor substrate in a cell region and in a peripheral circuit region. An offset spacer can be formed including a first material on the gate structures. A first ion implantation can be done using the gate structures and the offset spacer as an ion implantation mask to form source/drain regions. A material layer can be formed including a second material on the semiconductor substrate and on the gate structures. A material layer can be formed of a third material, having an etch selectivity with respect to the second material, on the material layer of the second material. An etch-back can be performed the material layer comprising the third material in the cell region and in the peripheral region, to simultaneously expose the source/drains region in the peripheral region and not expose the source/drain regions in the cell region.

Abstract: A semiconductor device includes a buried isolation pattern between an active pattern on which transistors are formed and a substrate. The active pattern has adjacent sections each extending longitudinally in a first direction. A field isolation pattern is interposed between the adjacent sections of the active pattern. The buried isolation pattern has sections spaced apart from each other in the first direction under each section of the active pattern. Each section of the buried isolation pattern extends from a lower portion of the field isolation pattern in a second direction perpendicular to the first direction. At least one gate structure is disposed on each section of the active pattern, and an impurity region is located adjacent to the gate structure at the upper surface of the active pattern. The impurity region is spaced from the buried isolation pattern in a third direction perpendicular to the first and second directions.

Abstract: A method of fabricating a semiconductor device can include forming gate structures for transistors on a semiconductor substrate in a cell region and in a peripheral circuit region, forming an offset spacer of a first material on the gate structure, performing first ion implantation for source/drain region formation using the gate structures and the offset spacer as an ion implantation mask, forming a material layer of a second material on the semiconductor substrate and the gate structures, forming a material layer of a third material, which has an etch selectivity with respect to the second material, on the material layer made of the second material, etching-back the material layer made of the third material using the material layer made of the second material as an etch stop layer to form a multi-layered spacer comprising the second material and the third material, performing second ion implantation for source/drain region formation using the gate structures and the multi-layered spacer as an ion implantati

Abstract: A semiconductor device includes a buried isolation pattern between an active pattern on which transistors are formed and a substrate. The active pattern has adjacent sections each extending longitudinally in a first direction. A field isolation pattern is interposed between the adjacent sections of the active pattern. The buried isolation pattern has sections spaced apart from each other in the first direction under each section of the active pattern. Each section of the buried isolation pattern extends from a lower portion of the field isolation pattern in a second direction perpendicular to the first direction. At least one gate structure is disposed on each section of the active pattern, and an impurity region is located adjacent to the gate structure at the upper surface of the active pattern. The impurity region is spaced from the buried isolation pattern in a third direction perpendicular to the first and second directions.