Patents by Inventor Jun Cheng

Jun Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240128219
    Abstract: A semiconductor die including mechanical-stress-resistant bump structures is provided. The semiconductor die includes dielectric material layers embedding metal interconnect structures, a connection pad-and-via structure, and a bump structure including a bump via portion and a bonding bump portion. The entirety of a bottom surface of the bump via portion is located within an area of a horizontal top surface of a pad portion of the connection pad-and-via structure.
    Type: Application
    Filed: December 6, 2023
    Publication date: April 18, 2024
    Inventors: Hui-Min Huang, Wei-Hung Lin, Kai Jun Zhan, Chang-Jung Hsueh, Wan-Yu Chiang, Ming-Da Cheng
  • Publication number: 20240125128
    Abstract: This invention discloses digitally printed plate, the manufacturing method and applications thereof, is characterized in that the digitally printed plate is of respectively from top to bottom surface lacquer layer, texture layer, second wear layer, first wear layer, pattern layer, bottom lacquer layer, base layer. The digitally printed plated has various patterns, with sufficient materials, printing unrepeatable stereoscopic pattern is possible, so it can satisfy customers' personalized customization requirements, without wasting abundant time or cost, and with process reduced, production efficiency is improved, enabling order manufacturing order insert and sample making at any time.
    Type: Application
    Filed: March 24, 2021
    Publication date: April 18, 2024
    Inventors: Jun Yuan, Quanshan Cheng, Juan Chen, Haiqing Qian, Rong Jiang, Yuan Liu
  • Patent number: 11961848
    Abstract: Disclosed are a display substrate and a manufacturing method therefor, and a display device. The display substrate comprises: a substrate base, and an active layer, a gate insulating layer, a first metal film layer, an interlayer insulating layer, a second metal film layer, and a passivation layer stacked in sequence on the substrate base. The first metal film layer comprises a pattern of a gate and a gate line. The second metal film layer comprises a pattern of a source/drain and a data line. The gate line and the data line are partially arranged opposite to each other. An oxide metal layer is provided on the surface of the side of the region of the gate line opposite to the data line facing the data line.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: April 16, 2024
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jun Liu, Liangchen Yan, Bin Zhou, Yadong Liang, Ning Liu, Leilei Cheng, Jingang Fang
  • Patent number: 11961817
    Abstract: An apparatus for forming a package structure is provided. The apparatus includes a processing chamber for bonding a first package component and a second package component. The apparatus also includes a bonding head disposed in the processing chamber. The bonding head includes a plurality of vacuum tubes communicating with a plurality of vacuum devices. The apparatus further includes a nozzle connected to the bonding head and configured to hold the second package component. The nozzle includes a plurality of first holes that overlap the vacuum tubes. The nozzle also includes a plurality of second holes offset from the first holes, wherein the second holes overlap at least two edges of the second package component. In addition, the apparatus includes a chuck table disposed in the processing chamber, and the chuck table is configured to hold and heat the first package component.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kai Jun Zhan, Chang-Jung Hsueh, Hui-Min Huang, Wei-Hung Lin, Ming-Da Cheng
  • Publication number: 20240122032
    Abstract: A display substrate including a drive-circuit layer and a light-emitting structure layer, a preparation method thereof, and a display device, the light-emitting structure layer includes an anode, a pixel definition layer, an organic light-emitting layer and a cathode, and an auxiliary electrode and an organic light-emitting block, arranged sequentially, the pixel definition layer includes an anode opening exposing the anode and an electrode opening exposing the auxiliary electrode, the organic light-emitting block is separated from the organic light-emitting layer, the auxiliary electrode includes the first, second and third auxiliary electrodes arranged sequentially; the cathode includes a first horizontal lapping part lapping with the first auxiliary electrode and a second sidewall lapping part lapping with the second auxiliary electrode, the thickness of the second sidewall lapping part in the direction parallel to the substrate is greater than that of the first horizontal lapping part in the direction per
    Type: Application
    Filed: April 21, 2021
    Publication date: April 11, 2024
    Inventors: Qinghe WANG, Bin ZHOU, Tongshang SU, Dacheng ZHANG, Jun WANG, Ning LIU, Yongchao HUANG, Jun CHENG, Liangchen YAN
  • Publication number: 20240101665
    Abstract: The invention discloses a monoclonal antibody against human GPR48 and application of the same. In the antibody provided by the present invention, the amino acid sequences of LCDR1, LCDR2, and LCDR3 in the light chain variable region are shown in positions 27-32, 50-52, and 89-97 of SEQ ID No.1 sequentially, and the amino acid sequences of HCDR1, HCDR2 and HCDR3 in the heavy chain variable region are shown in positions 26-33, 51-60 and 99-108 of SEQ ID No.2 sequentially. The antibody has strong specificity and sensitivity to GPR48 protein, and can be applied to immunological experimental techniques such as western blotting, immunofluorescence and immunohistochemistry; it can be applied to flow cytometry experimental techniques such as flow cyometry analysis and flow cytometry sorting; it can be applied to the scientific research of signaling pathways such as subcellular localization and protein interaction.
    Type: Application
    Filed: January 28, 2022
    Publication date: March 28, 2024
    Inventors: Quan CHEN, Lei DU, Qi CHENG, Hao ZHENG, Jun WANG, Xiaohui WANG, Lei LIU
  • Patent number: 11941844
    Abstract: An object detection model generation method as well as an electronic device and a computer readable storage medium using the same are provided. The method includes: during the iterative training of the to-be-trained object detection model, the detection accuracy of the iteration nodes of the object detection model is sequentially determined according to the node order, and the mis-detected negative samples of the object detection model at the iteration nodes with the detection accuracy less than or equal to a preset threshold are enhanced. Then the object detection model is trained at the iteration node based on the enhanced negative samples and a first amount of preset training samples. After the training at the iteration nodes are completed, it returns to the step of sequentially determining the detection accuracy of the iteration nodes of the object detection model until the training of the object detection model is completed.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: March 26, 2024
    Assignee: UBTECH ROBOTICS CORP LTD
    Inventors: Yepeng Liu, Yusheng Zeng, Jun Cheng, Jing Gu, Yue Wang, Jianxin Pang
  • Publication number: 20240096491
    Abstract: A computer readable storage medium is provided. When contents of the computer readable storage medium are executed by a processor, multi-photon imaging may be performed on a histopathological section containing tumor environment information, and pathological partitioning of a tumor microenvironment may be further performed through image processing. A value of each collagen feature parameters, such as a morphological feature parameter, an energy feature parameter and a texture feature parameter, may be extracted from a tumor tissue region, an invasive margin (IM) region and a normal tissue (N) region. An inter-region difference and a variation may be calculated according to feature parameters of regions. A collagen feature scoring model may be established. A collagen feature score may be calculated with the collagen feature parameters input to the model.
    Type: Application
    Filed: November 15, 2022
    Publication date: March 21, 2024
    Inventors: Jun YAN, Shumin DONG, Botao YAN, Weisheng CHEN, Xiaoyu DONG, Xiumin LIU, Shuhan ZHAO, Jiaxin CHENG, Yanfeng DONG, Wei JIANG, Dexin CHEN, Guoxin LI
  • Publication number: 20240091716
    Abstract: An electrolytic eluent generator includes an electrolyte reservoir, an eluent generation chamber, and an ion exchange membrane stack. The electrolyte reservoir includes a chamber containing an aqueous electrolyte solution including an electrolyte; and a first electrode. The eluent generation chamber including a second electrode. The ion exchange connector includes an ion exchange membrane stack, and a compression block.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 21, 2024
    Inventors: Zhongqing LU, Yan LIU, Christopher A. POHL, Jinhua CHEN, Jun CHENG
  • Patent number: 11933645
    Abstract: Methods and apparatus to determine a position of a rotatable shaft of a motor are disclosed. An example apparatus to determine a position of a rotatable shaft of a motor includes a sensor printed circuit board (PCB) structured to be mounted to a motor, the sensor PCB including a plurality of capacitive sensors, the plurality of capacitive sensors having respective ones of a plurality of capacitances that independently change as a conductor moves relative to the sensor PCB in conjunction with a rotatable shaft of the motor during an operation of the motor, and a controller electrically coupled to the sensor PCB, the controller configured to determine a position of the rotatable shaft based on the plurality of capacitances.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: March 19, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Rujun Ji, Jun Zhang, Lichang Cheng, Kangcheng Xu
  • Publication number: 20240084447
    Abstract: A sealing article includes a body and a coating layer disposed on at least one surface of the body. The body comprises a polymeric elastomer such as perfluoroelastomer or fluoroelastomer. The coating layer comprises at least one metal. The sealing article may be a seal, a gasket, an O-ring, a T-ring or any other suitable product. The sealing article is resistant to ultra-violet (UV) light and plasma, and may be used for sealing a semiconductor processing chamber.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 14, 2024
    Inventors: Peng-Cheng Hong, Jun-Liang Pu, W.L. Hsu, Chung-Hao Kao, Chia-Chun Hung, Cheng-Yi Wu, Chin-Szu Lee
  • Publication number: 20240086716
    Abstract: A method for training a deep neural network (DNN) capable of adversarial detection. The DNN is configured with a plurality of sets of weights candidates. The method includes inputting training data selected from training data set to the DNN. The method further includes calculating, based on the training data, a first term for indicating a difference between a variational posterior probability distribution and a true posterior probability distribution of the DNN. The method further includes perturbing the training data to generate perturbed training data; and calculating a second term for indicating a quantification of predictive uncertainty on the perturbed training data. The method further includes updating the plurality of sets of weights candidates of the DNN based on augmenting the summation of the first term and the second term.
    Type: Application
    Filed: February 26, 2021
    Publication date: March 14, 2024
    Inventors: Hang Su, Jun Zhu, Zhijie Deng, Ze Cheng
  • Publication number: 20240090230
    Abstract: A memory array and an operation method of the memory array are provided. The memory array includes first and second ferroelectric memory devices formed along a gate electrode, a channel layer and a ferroelectric layer between the gate electrode and the channel layer. The ferroelectric memory devices include: a common source/drain electrode and two respective source/drain electrodes, separately in contact with a side of the channel layer opposite to the ferroelectric layer, wherein the common source/drain electrode is disposed between the respective source/drain electrodes; and first and second auxiliary gates, capacitively coupled to the channel layer, wherein the first auxiliary gate is located between the common source/drain electrode and one of the respective source/drain electrodes, and the second auxiliary gate is located between the common source/drain electrode and the other respective source/drain electrode.
    Type: Application
    Filed: January 9, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Ling Lu, Chen-Jun Wu, Ya-Yun Cheng, Sheng-Chih Lai, Yi-Ching Liu, Yu-Ming Lin, Feng-Cheng Yang, Chung-Te Lin
  • Publication number: 20240081352
    Abstract: The present disclosure provides a blending method of high-quality and dual-purpose flour for bread and noodles, belonging to the technical field of flour processing. The method includes: selecting flour of a high-quality and dual-purpose wheat variety for bread and noodles as a high-quality basic flour for blending; according to a large gradient experimental design, selecting a gradient range ratio with a sedimentation value ?46.0 mL and a dough development time ?9.6 min, followed by subdividing for small gradient experiments; selecting a ratio with flour sedimentation value and dough development time that reach an ideal value to blend a large amount of flour; and making bread and noodles for scoring, followed by determining a blending ratio if a scoring result reaches an ideal value.
    Type: Application
    Filed: September 11, 2022
    Publication date: March 14, 2024
    Inventors: Yan Zi, Jianmin Song, Xiao Ma, Aifeng Liu, Wei Ju, Haosheng Li, Dungong Cheng, Canguo Wang, Jun Guo, Jianjun Liu, Xinyou Cao, Cheng Liu, Shengnan Zhai, Faji Li, Ran Han, Zhendong Zhao
  • Patent number: 11930677
    Abstract: A display panel and a fabricating method thereof, and a displaying device. The display panel includes a substrate, a resistance reducing trace, an inter-layer-medium layer and a signal line. The substrate is divided into a plurality of sub-pixel regions and a pixel separating region. The resistance reducing trace is provided on the pixel separating region of the substrate. The inter-layer-medium layer is provided on the substrate, and the inter-layer-medium layer has an opening exposing the resistance reducing trace. The signal line is provided within the opening, the signal line is connected to the resistance reducing trace, the signal line is distributed in a column direction along the display panel, and in a row direction along the display panel, a width of the opening is greater than or equal to a width of the signal line.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: March 12, 2024
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yongchao Huang, Can Yuan, Liusong Ni, Chao Wang, Jiawen Song, Zhiwen Luo, Jun Liu, Leilei Cheng, Qinghe Wang, Tao Sun
  • Patent number: 11930679
    Abstract: The present disclosure relates to the technical field of display, and discloses an array substrate, a preparation method therefor, and a display device. When dielectric layers, such as a buffer layer, an interlayer dielectric layer, and a gate insulation layer, are formed between a source-drain electrode and a substrate, the thickness of at least one dielectric layer among said dielectric layers underneath a first through hole for connecting a drain electrode and an anode is increased, which is to say that the drain electrode is raised to be further away from the substrate, causing the drain electrode to be closer to a surface of a planarization layer that faces away from the substrate, i.e., reducing the thickness of a portion of the planarization layer above the drain electrode.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: March 12, 2024
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jingang Fang, Luke Ding, Jun Liu, Bin Zhou, Jun Cheng
  • Publication number: 20240078445
    Abstract: The application relates to a method for developing the agitation system of a scale-up polymerization vessel. A simulated prediction model is obtained by use of a small polymerization vessel and by integrating Taguchi experimental design method with artificial intelligence (AI) neural network. Accordingly, vessel parameters for the agitation system of a scale-up polymerization vessel can be rapidly and accurately predicted based on simulation qualities thereof, further facilitating a construction of the agitation system of a scale-up polymerization vessel.
    Type: Application
    Filed: July 6, 2023
    Publication date: March 7, 2024
    Inventors: Fuh-Yih SHIH, Shih-Ming YEH, Yu-Cheng CHEN, Jun-Teng CHEN
  • Patent number: 11920238
    Abstract: A method of making a sealing article that includes a body and a coating layer disposed on at least one surface of the body. The body comprises a polymeric elastomer such as perfluoroelastomer or fluoroelastomer. The coating layer comprises at least one metal. The sealing article may be a seal, a gasket, an O-ring, a T-ring or any other suitable product. The sealing article is resistant to ultra-violet (UV) light and plasma, and may be used for sealing a semiconductor processing chamber.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Peng-Cheng Hong, Jun-Liang Pu, W. L. Hsu, Chung-Hao Kao, Chia-Chun Hung, Cheng-Yi Wu, Chin-Szu Lee
  • Patent number: 11924965
    Abstract: A package component and forming method thereof are provided. The package component includes a substrate and a conductive layer. The substrate includes a first surface. The conductive layer is disposed over the first surface. The conductive layer includes a first conductive feature and a second conductive feature. The second conductive feature covers a portion of the first conductive feature. A resistance of the second conductive feature is lower than a resistance of the first conductive feature.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun-Wei Chang, Jian-Hong Lin, Shu-Yuan Ku, Wei-Cheng Liu, Yinlung Lu, Jun He
  • Patent number: D1017061
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: March 5, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chih-Hsien Wang, Shih-Chieh Chang, Yan-Jun Wang, Peng-Hui Wang, Ming-Chieh Cheng