Patents by Inventor Jun-Chi Huang
Jun-Chi Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240087644Abstract: A forming operation of resistive memory device is provided. The operation includes: applying a pre-forming gate voltage and a pre-forming bit line voltage to a target memory cell; performing a dense switching forming operation, wherein the dense switching forming operation includes alternately performing dense set operations and dense reset operations on the target memory cell, wherein the dense set operation includes applying a dense switching gate voltage and a dense set bit line voltage; and performing a normal set operation on the target memory cell, wherein the normal set operation includes applying a normal set gate voltage and a normal set bit line voltage to the target memory cell, the normal set gate voltage is greater than the pre-forming gate voltage and the dense switching gate voltage, and the normal set bit line voltage is less than the pre-forming bit line voltage and the dense set bit line voltage.Type: ApplicationFiled: August 29, 2023Publication date: March 14, 2024Applicant: Winbond Electronics Corp.Inventors: I-Hsien Tseng, Lung-Chi Cheng, Ju-Chieh Cheng, Jun-Yao Huang, Ping-Kun Wang
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Patent number: 9355848Abstract: A semiconductor structure and a method for forming the same are provided. The method includes following steps. A gate electrode layer is formed on a substrate. A spacer structure is formed on a sidewall of the gate electrode layer. A dielectric cap film is formed to cover the gate electrode layer and the spacer structure. A source/drain implantation is performed to the substrate with the dielectric cap film exposed to a condition of the source/drain implantation.Type: GrantFiled: October 18, 2013Date of Patent: May 31, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wei-Chih Chen, Chung-Hsien Tsai, Tung-Ming Chen, Chih-Sheng Chang, Jun-Chi Huang, Chih-Jen Lin, Yu-Hsiang Lin
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Publication number: 20150108587Abstract: A semiconductor structure and a method for forming the same are provided. The method includes following steps. A gate electrode layer is formed on a substrate. A spacer structure is formed on a sidewall of the gate electrode layer. A dielectric cap film is formed to cover the gate electrode layer and the spacer structure. A source/drain implantation is performed to the substrate with the dielectric cap film exposed to a condition of the source/drain implantation.Type: ApplicationFiled: October 18, 2013Publication date: April 23, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: Wei-Chih Chen, Chung-Hsien Tsai, Tung-Ming Chen, Chih-Sheng Chang, Jun-Chi Huang, Chih-Jen Lin, Yu-Hsiang Lin
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Patent number: 8546962Abstract: A mark structure for measuring the alignment accuracy between a former layer and a latter layer with electron beam inspection (EBI) is described. The mark structure includes multiple divisions, each of which includes at least one region that includes multiple parts each disposed with a pair of a pattern of the former layer and a pattern of the latter layer. In each region, all of the parts have the same distance in a direction between the pattern of the former layer and the pattern of the latter layer. The distance in the direction is varied over the regions of the divisions of the mark structure.Type: GrantFiled: March 8, 2011Date of Patent: October 1, 2013Assignee: United Microelectronics Corp.Inventors: Jun-Chi Huang, Po-Chao Tsao, Ming-Te Wei
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Patent number: 8415732Abstract: A method for fabricating a trench capacitor is disclosed. A substrate having a first pad layer is provided. STI structure is embedded into the first pad layer and the substrate. A second pad layer is deposited over the first pad layer and the STI structure. Two adjacent trenches are etched into the first, second pad layers, and the semiconductor substrate. The second pad layer and a portion of the STI structure between the two trenches are etched to form a ridge. A liner is formed on interior surface of the trenches. A first polysilicon layer is formed on the liner. A capacitor dielectric layer is formed on the first polysilicon layer. The two adjacent trenches are filled with a second polysilicon layer. The second polysilicon layer is then etched until the capacitor dielectric layer is exposed. The fabrication process is easy to integrate to SoC chip.Type: GrantFiled: October 30, 2007Date of Patent: April 9, 2013Assignee: United Microelectronics Corp.Inventors: Yi-Nan Su, Yung-Chang Lin, Jun-Chi Huang
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Publication number: 20120229807Abstract: A mark structure for measuring the alignment accuracy between a former layer and a latter layer with electron beam inspection (EBI) is described. The mark structure includes multiple divisions, each of which includes at least one region that includes multiple parts each disposed with a pair of a pattern of the former layer and a pattern of the latter layer. In each region, all of the parts have the same distance in a direction between the pattern of the former layer and the pattern of the latter layer. The distance in the direction is varied over the regions of the divisions of the mark structure.Type: ApplicationFiled: March 8, 2011Publication date: September 13, 2012Applicant: United Microelectronics Corp.Inventors: JUN-CHI HUANG, Po-Chao Tsao, Ming-Te Wei
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Publication number: 20110309424Abstract: A structure of a memory cell of a static random memory device and a process for fabricating the same are disclosed. The memory cell includes a substrate having an active region including an N-well and a shallow trench isolation structure; a first gate and a second gate formed over the substrate; a halo region, a LLD, and a source and drain region formed on two sides of the first gate; an interlevel dielectric layer covering the substrate, the first and second gates; and a contact penetrating the interlevel dielectric layer and extending to the source and drain region, no halo region is formed under the contact.Type: ApplicationFiled: June 21, 2010Publication date: December 22, 2011Inventors: Ming-Te WEI, Po-Chao Tsao, Jun-Chi Huang, Chia-Wei Huang, Chuan-Hsien Fu, Chih-Fang Tsai, Te-Hung Wu
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Patent number: 7566932Abstract: A static random access memory (SRAM) unit comprising a substrate, a gate dielectric layer, a gate, a trench capacitor, a pair of source/drain regions, a first contact and a second contact is provided. The substrate has a trench formed therein. The gate dielectric layer is disposed on the substrate and the gate is disposed on the gate dielectric layer. The trench capacitor is disposed in the trench near one side of the gate. The source/drain regions are disposed in the substrate near the respective sides of the gate with one of the source/drain region positioned between the gate and the trench capacitor. The first contact is electrically connected to the trench capacitor and the second contact is electrically connected to the other source/drain region.Type: GrantFiled: March 20, 2006Date of Patent: July 28, 2009Assignee: United Microelectronics Corp.Inventors: Jun-Chi Huang, Chia-Wen Liang, Yung-Chang Lin, Richard Lee
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Patent number: 7563671Abstract: A method for forming a trench capacitor and memory cell by providing a substrate on which a grid STI and a plurality of active regions covered by a hard mask layer are formed. A photoresist is formed and a low grade photo mask having only X direction consideration is used to define the required pattern on the photoresist. The hard mask layer and the STI are used as an etching mask to etch a plurality of deep trenches. Then diffusion regions, capacitor dielectric layer, and polysilicon filled to form the capacitor bottom electrode are sequentially formed to complete the forming for trench capacitors. After removing the hard mask layer and performing a logic process, the memory cells are completed.Type: GrantFiled: November 22, 2007Date of Patent: July 21, 2009Assignee: United Microelectronics Corp.Inventors: Yi-Nan Su, Jun-Chi Huang
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Patent number: 7541634Abstract: A trench capacitor including a substrate, at least a group of capacitor units, an isolation structure and a conductive layer is described. The substrate includes a first trench and a second trench. The group of capacitor units is disposed in the substrate. The group of capacitor units includes a first capacitor disposed in the first trench and a second capacitor disposed in the second trench. The isolation structure is disposed in the substrate between the first capacitor and the second capacitor. The conductive layer is disposed in the substrate above the isolation structure and electrically connected to the first upper electrode and the second upper electrode.Type: GrantFiled: January 31, 2007Date of Patent: June 2, 2009Assignee: United Microelectronics Corp.Inventors: Yi-Nan Su, Jun-Chi Huang
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Patent number: 7407852Abstract: A method of fabricating trench capacitors is described. A substrate having at least one isolation structure is provided. A first trench and a second trench are formed in the substrate beside the isolation structure. A first lower electrode and a second lower electrode are formed in the substrate around the first trench and the second trench. A first capacitor dielectric layer and a second capacitor dielectric layer are formed on the respective surfaces of the first trench and the second trench. A first upper electrode and a second upper electrode are formed to fill the first trench and the second trench. A portion of the isolation structure between the first trench and the second trench is removed to form an opening. A conductive layer is formed to fill the opening and connect electrically with the first upper electrode and the second upper electrode.Type: GrantFiled: August 16, 2005Date of Patent: August 5, 2008Assignee: United Microelectronics Corp.Inventors: Yi-Nan Su, Jun-Chi Huang
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Patent number: 7351634Abstract: A method for fabricating a trench capacitor is disclosed. A substrate having a first pad layer is provided. STI structure is embedded into the first pad layer and the substrate. A second pad layer is deposited over the first pad layer and the STI structure. Two adjacent trenches are etched into the first, second pad layers, and the semiconductor substrate. The second pad layer and a portion of the STI structure between the two trenches are etched to form a ridge. A liner is formed on interior surface of the trenches. A first polysilicon layer is formed on the liner. A capacitor dielectric layer is formed on the first polysilicon layer. The two adjacent trenches are filled with a second polysilicon layer. The second polysilicon layer is then etched until the capacitor dielectric layer is exposed. The fabrication process is easy to integrate to SoC chip.Type: GrantFiled: May 25, 2006Date of Patent: April 1, 2008Assignee: United Microelectronics Corp.Inventors: Yi-Nan Su, Yung-Chang Lin, Jun-Chi Huang
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Publication number: 20080070374Abstract: A method for forming a trench capacitor and memory cell by providing a substrate on which a grid STI and a plurality of active regions covered by a hard mask layer are formed. A photoresist is formed and a low grade photo mask having only X direction consideration is used to define the required pattern on the photoresist. The hard mask layer and the STI are used as an etching mask to etch a plurality of deep trenches. Then diffusion regions, capacitor dielectric layer, and polysilicon filled to form the capacitor bottom electrode are sequentially formed to complete the forming for trench capacitors. After removing the hard mask layer and performing a logic process, the memory cells are completed.Type: ApplicationFiled: November 22, 2007Publication date: March 20, 2008Inventors: Yi-Nan Su, Jun-Chi Huang
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Publication number: 20080048232Abstract: A method for fabricating a trench capacitor is disclosed. A substrate having a first pad layer is provided. STI structure is embedded into the first pad layer and the substrate. A second pad layer is deposited over the first pad layer and the STI structure. Two adjacent trenches are etched into the first, second pad layers, and the semiconductor substrate. The second pad layer and a portion of the STI structure between the two trenches are etched to form a ridge. A liner is formed on interior surface of the trenches. A first polysilicon layer is formed on the liner. A capacitor dielectric layer is formed on the first polysilicon layer. The two adjacent trenches are filled with a second polysilicon layer. The second polysilicon layer is then etched until the capacitor dielectric layer is exposed. The fabrication process is easy to integrate to SoC chip.Type: ApplicationFiled: October 30, 2007Publication date: February 28, 2008Inventors: Yi-Nan Su, Yung-Chang Lin, Jun-Chi Huang
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Patent number: 7335553Abstract: A method for forming a trench capacitor and memory cell by providing a substrate on which a grid STI and a plurality of active regions covered by a hard mask layer are formed. A photoresist is formed and a low grade photo mask having only X direction consideration is used to define the required pattern on the photoresist. The hard mask layer and the STI are used as an etching mask to etch a plurality of deep trenches. Then diffusion regions, capacitor dielectric layer, and polysilicon filled to form the capacitor bottom electrode are sequentially formed to complete the forming for trench capacitors. After removing the hard mask layer and performing a logic process, the memory cells are completed.Type: GrantFiled: September 14, 2005Date of Patent: February 26, 2008Assignee: United Microelectronics Corp.Inventors: Yi-Nan Su, Jun-Chi Huang
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Publication number: 20080020539Abstract: A dynamic random access memory including a substrate, an isolation structure, two transistors, two trench capacitors and two passing gates is provided. The isolation structure, including a first isolation structure and a second isolation structure, is disposed in the substrate. The second isolation structure is disposed in the substrate above the first isolation structure and the bottom surface of the second isolation structure is lower than the top surface of the substrate. The periphery of the second isolation structure is beyond that of the first isolation structure. The transistors are disposed on the substrate respectively at two sides of the isolation structure. The trench capacitors are respectively disposed between the transistors and the isolation structures. A portion of the second isolation structure is disposed in the trench capacitor. The passing gates are completely disposed on the second isolation structure.Type: ApplicationFiled: October 1, 2007Publication date: January 24, 2008Inventors: CHIEN-KUO WANG, JUN-CHI HUANG, RUEY-CHYR LEE, YUNG-CHANG LIN
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Publication number: 20070275523Abstract: A method for fabricating a trench capacitor is disclosed. A substrate having a first pad layer is provided. STI structure is embedded into the first pad layer and the substrate. A second pad layer is deposited over the first pad layer and the STI structure. Two adjacent trenches are etched into the first, second pad layers, and the semiconductor substrate. The second pad layer and a portion of the STI structure between the two trenches are etched to form a ridge. A liner is formed on interior surface of the trenches. A first polysilicon layer is formed on the liner. A capacitor dielectric layer is formed on the first polysilicon layer. The two adjacent trenches are filled with a second polysilicon layer. The second polysilicon layer is then etched until the capacitor dielectric layer is exposed. The fabrication process is easy to integrate to SoC chip.Type: ApplicationFiled: May 25, 2006Publication date: November 29, 2007Inventors: Yi-Nan Su, Yung-Chang Lin, Jun-Chi Huang
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Publication number: 20070269946Abstract: A dynamic random access memory including a substrate, an isolation structure, two transistors, two trench capacitors and two passing gates is provided. The isolation structure, including a first isolation structure and a second isolation structure, is disposed in the substrate. The second isolation structure is disposed in the substrate above the first isolation structure and the bottom surface of the second isolation structure is lower than the top surface of the substrate. The periphery of the second isolation structure is beyond that of the first isolation structure. The transistors are disposed on the substrate respectively at two sides of the isolation structure. The trench capacitors are respectively disposed between the transistors and the isolation structures. A portion of the second isolation structure is disposed in the trench capacitor. The passing gates are completely disposed on the second isolation structure.Type: ApplicationFiled: May 19, 2006Publication date: November 22, 2007Inventors: Chien-Kuo Wang, Jun-Chi Huang, Ruey-Chyr Lee, Yung-Chang Lin
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Publication number: 20070215937Abstract: A static random access memory (SRAM) unit comprising a substrate, a gate dielectric layer, a gate, a trench capacitor, a pair of source/drain regions, a first contact and a second contact is provided. The substrate has a trench formed therein. The gate dielectric layer is disposed on the substrate and the gate is disposed on the gate dielectric layer. The trench capacitor is disposed in the trench near one side of the gate. The source/drain regions are disposed in the substrate near the respective sides of the gate with one of the source/drain region positioned between the gate and the trench capacitor. The first contact is electrically connected to the trench capacitor and the second contact is electrically connected to the other source/drain region.Type: ApplicationFiled: March 20, 2006Publication date: September 20, 2007Inventors: Jun-Chi Huang, Chia-Wen Liang, Yung-Chang Lin, Richard Lee
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Publication number: 20070120169Abstract: A trench capacitor including a substrate, at least a group of capacitor units, an isolation structure and a conductive layer is described. The substrate includes a first trench and a second trench. The group of capacitor units is disposed in the substrate. The group of capacitor units includes a first capacitor disposed in the first trench and a second capacitor disposed in the second trench. The isolation structure is disposed in the substrate between the first capacitor and the second capacitor. The conductive layer is disposed in the substrate above the isolation structure and electrically connected to the first upper electrode and the second upper electrode.Type: ApplicationFiled: January 31, 2007Publication date: May 31, 2007Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yi-Nan Su, Jun-Chi Huang