Patents by Inventor Jun-Chul Kim
Jun-Chul Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250087092Abstract: Disclosed are a three-dimensional (3D) simulation method and a 3D simulation apparatus. The 3D simulation method disclosed herein includes a step (S20) of separating point cloud data including a road, an obstacle, and a cargo transportation route into road data and obstacle data, a step (S40) of converting the road data into road mesh data, and converting the obstacle data into obstacle mesh data, a step (S60) of constructing a virtual environment by merging the road mesh data with the obstacle mesh data, a step (S80) of loading a specific cargo transportation route to the virtual environment, a step (S100) of loading a 3D transport truck and a 3D cargo to a predetermined point of the cargo transportation route, and a step (S120) of performing a route survey simulation while virtually driving the 3D transport truck and the 3D cargo along the cargo transportation route.Type: ApplicationFiled: December 4, 2023Publication date: March 13, 2025Applicants: SAMSUNG E&A CO., LTD., Morai Inc.Inventors: Jun Chul HWANG, Sung Il KIM, Yong Ho AHN, Jae Hun CHOI, Taek Sun LEE, Hwang JEON, Jun HONG, Ji Won JUNG
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Publication number: 20250079135Abstract: A deposition apparatus including: a base substrate; an electrostatic chuck on the base substrate; and a plate on the electrostatic chuck. The plate has a first area in which first magnet units are arranged and a second area in which second magnet units are arranged. The first magnet units are spaced apart from each other at a first distance, and the second magnet units are spaced apart from each other at a second distance. The second distance is greater than the first distance.Type: ApplicationFiled: June 10, 2024Publication date: March 6, 2025Inventors: Jun Hyeuk KO, Jong Bum KIM, Young Kwang LEE, Min Goo KANG, Suk Ha RYU, Min Chul SONG, Min A WOO
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Publication number: 20250072019Abstract: Disclosed herein are a Schottky barrier diode (SBD) and a method of manufacturing the same. The SBD includes a substrate, an ohmic layer formed on a portion of an upper portion of the substrate, a Schottky layer formed on a portion of an upper portion of the ohmic layer, an insulating layer formed on a portion of the upper portion of the ohmic layer, a low-k material layer formed on a portion of the upper portion of the substrate, and a Schottky metal layer formed on portions of upper portions of the low-k material layer and the insulating layer.Type: ApplicationFiled: July 11, 2024Publication date: February 27, 2025Inventors: Jun Hwan SHIN, Young Ho Kim, Eui Su Lee, Jin Chul Cho, Soo Cheol Kang, Dong Woo Park, II Min Lee
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Publication number: 20250062238Abstract: A semiconductor package is provided. The semiconductor package comprises a package substrate, a first semiconductor chip on the package substrate, a second semiconductor chip spaced apart from the first semiconductor chip on the package substrate, and a bridge die placed below the first semiconductor chip and the second semiconductor chip on the package substrate, wherein the bridge die includes a first face that faces the first semiconductor chip and the second semiconductor chip, a second face that faces the package substrate, a connection wiring structure which is placed on the first face, and connects the first semiconductor chip and the second semiconductor chip, and a power wiring structure which is placed on the second face, and provides power to the first semiconductor chip and the second semiconductor chip.Type: ApplicationFiled: February 26, 2024Publication date: February 20, 2025Applicant: Samsung Electronics Co., Ltd.Inventors: Bong Wee YU, Chang Soo KIM, Byung Chul JEON, Jun Ho HUH
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Patent number: 12230816Abstract: A secondary battery case includes a recess part recessed downward, and a sealing part provided around the recess part when the secondary battery case is unfolded. At least portions of the sealing part are attached to each other to seal inner surfaces of the recess part from an outside. A secondary battery includes an electrode assembly and the secondary battery case. The recess part of the secondary battery case has a width that corresponds to a thickness of the electrode assembly.Type: GrantFiled: February 27, 2020Date of Patent: February 18, 2025Assignee: LG Energy Solution, Ltd.Inventors: Hyun Beom Kim, Jun Kyu Park, Jeong Min Ha, Gi Man Kim, Hyun Chul Ha
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Publication number: 20250056993Abstract: A display device includes a substrate including sub-pixel circuit areas that are arranged in m rows and n columns, where m and n are positive integers, first gate lines extending in a row direction, data lines extending in a column direction, initialization power lines extending in the row direction, including first power lines disposed in sub-pixel circuit areas of odd rows and receiving a first initialization voltage and second power lines disposed in sub-pixel circuit areas of even rows and receiving a second initialization voltage, and transmission lines extending in the column direction, including first transmission lines disposed in sub-pixel circuit areas of odd columns and receiving the first initialization voltage from the first power lines and second transmission lines disposed in sub-pixel circuit areas of even columns and receiving the second initialization voltage from the second power lines.Type: ApplicationFiled: October 21, 2024Publication date: February 13, 2025Inventors: JUN-YONG AN, MIN JEONG KIM, HYUNGJUN PARK, NUREE UM, KWANG-CHUL JUNG
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Patent number: 12209149Abstract: A continuous preparation system of a conjugated diene-based polymer having improved rolling resistance properties is provided. By utilizing the continuous preparation system a polymerization conversion ratio at an initial stage of polymerization is easy to control, long time operation is possible and productivity is excellent.Type: GrantFiled: December 24, 2020Date of Patent: January 28, 2025Assignee: LG Chem, Ltd.Inventors: Tae Chul Lee, Su Hwa Kim, No Ma Kim, Jun Seok Ko
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Patent number: 12014881Abstract: The present invention provides a method for manufacturing a high frequency capacitor, including preparing a substrate for formation of the capacitor, forming a dielectric layer at an upper surface of the substrate, forming an upper electrode at an upper surface of the dielectric layer, and removing a portion of a lower surface of the substrate, to expose a lower surface of the dielectric layer, and forming a lower electrode at the lower surface of the dielectric layer. The high frequency capacitor includes a dielectric layer having a uniform surface, a thick upper electrode, and a thick lower electrode and, as such, exhibits high quality factor (Q) even at a high frequency.Type: GrantFiled: March 30, 2022Date of Patent: June 18, 2024Assignee: KOREA ELECTRONICS TECHNOLOGY INSTITUTEInventors: Jong Min Yook, Je In Yu, Jun Chul Kim, Dong Su Kim
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Patent number: 11658374Abstract: A quasi-coaxial transmission line, a semiconductor package including the same and a method of manufacturing the same are disclosed. The quasi-coaxial transmission line includes a core, which is formed through an upper surface and a lower surface of a base substrate so as to transmit an electrical signal, and a shield, which is spaced apart from the core and which coaxially surrounds a side surface of the core, at least a portion of the shield being removed so as to form an open portion. The quasi-coaxial transmission line is capable of preventing distortion of an electrical signal at a portion thereof that is connected to an external circuit board and to reduce an area of a semiconductor package including the quasi-coaxial transmission line.Type: GrantFiled: May 12, 2020Date of Patent: May 23, 2023Assignee: KOREA ELECTRONICS TECHNOLOGY INSTITUTEInventors: Jong Min Yook, Jun Chul Kim, Dong Su Kim
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Semiconductor package including passive device embedded therein and method of manufacturing the same
Patent number: 11538770Abstract: A semiconductor package includes a semiconductor chip including an electrode pad formed on the top surface thereof, a passive device embedded in the semiconductor package, the passive device having no functional electrode on the top surface thereof, a cover layer covering the semiconductor chip and the passive device, and at least one electrode pattern formed on the cover layer to transmit electrical signals. The cover layer includes at least one first opening formed to expose a region in which the functional electrode is to be formed. The electrode pattern includes a functional electrode portion formed in a region in which the functional electrode of the passive device is to be formed through the first opening. In the process of forming the electrode pattern, a functional electrode of the passive device is formed together therewith, thereby eliminating a separate step of manufacturing a functional electrode and thus reducing manufacturing costs.Type: GrantFiled: May 20, 2020Date of Patent: December 27, 2022Assignee: Korea Electronics Technology InstituteInventors: Jong Min Yook, Jun Chul Kim, Dong Su Kim -
Publication number: 20220328253Abstract: The present invention provides a method for manufacturing a high frequency capacitor, including preparing a substrate for formation of the capacitor, forming a dielectric layer at an upper surface of the substrate, forming an upper electrode at an upper surface of the dielectric layer, and removing a portion of a lower surface of the substrate, to expose a lower surface of the dielectric layer, and forming a lower electrode at the lower surface of the dielectric layer. The high frequency capacitor includes a dielectric layer having a uniform surface, a thick upper electrode, and a thick lower electrode and, as such, exhibits high quality factor (Q) even at a high frequency.Type: ApplicationFiled: March 30, 2022Publication date: October 13, 2022Inventors: Jong Min YOOK, Je In YU, Jun Chul KIM, Dong Su KIM
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Patent number: 11197372Abstract: An embodiment of the present invention provides a capacitor having a through hole structure and a manufacturing method therefor. The capacitor having the through hole structure includes: a baseboard having a through hole penetrating from an upper surface of the baseboard to a lower surface thereof; a first conductive layer formed on an internal surface of the through hole, and the upper surface of the baseboard, the lower surface thereof, or both the upper and lower surfaces thereof; a first dielectric layer formed on the first conductive layer; and a second conductive layer formed on the first dielectric layer.Type: GrantFiled: October 23, 2019Date of Patent: December 7, 2021Assignee: KOREA ELECTRONICS TECHNOLOGY INSTITUTEInventors: Jong Min Yook, Jun Chul Kim, Dong Su Kim
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Publication number: 20200381797Abstract: A quasi-coaxial transmission line, a semiconductor package including the same and a method of manufacturing the same are disclosed. The quasi-coaxial transmission line includes a core, which is formed through an upper surface and a lower surface of a base substrate so as to transmit an electrical signal, and a shield, which is spaced apart from the core and which coaxially surrounds a side surface of the core, at least a portion of the shield being removed so as to form an open portion. The quasi-coaxial transmission line is capable of preventing distortion of an electrical signal at a portion thereof that is connected to an external circuit board and to reduce an area of a semiconductor package including the quasi-coaxial transmission line.Type: ApplicationFiled: May 12, 2020Publication date: December 3, 2020Inventors: Jong Min YOOK, Jun Chul KIM, Dong Su KIM
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SEMICONDUCTOR PACKAGE INCLUDING PASSIVE DEVICE EMBEDDED THEREIN AND METHOD OF MANUFACTURING THE SAME
Publication number: 20200373256Abstract: A semiconductor package includes a semiconductor chip including an electrode pad formed on the top surface thereof, a passive device embedded in the semiconductor package, the passive device having no functional electrode on the top surface thereof, a cover layer covering the semiconductor chip and the passive device, and at least one electrode pattern formed on the cover layer to transmit electrical signals. The cover layer includes at least one first opening formed to expose a region in which the functional electrode is to be formed. The electrode pattern includes a functional electrode portion formed in a region in which the functional electrode of the passive device is to be formed through the first opening. In the process of forming the electrode pattern, a functional electrode of the passive device is formed together therewith, thereby eliminating a separate step of manufacturing a functional electrode and thus reducing manufacturing costs.Type: ApplicationFiled: May 20, 2020Publication date: November 26, 2020Applicant: Korea Electronics Technology InstituteInventors: Jong Min YOOK, Jun Chul KIM, Dong Su KIM -
Publication number: 20200137889Abstract: An embodiment of the present invention provides a capacitor having a through hole structure and a manufacturing method therefor. The capacitor having the through hole structure includes: a baseboard having a through hole penetrating from an upper surface of the baseboard to a lower surface thereof; a first conductive layer formed on an internal surface of the through hole, and the upper surface of the baseboard, the lower surface thereof, or both the upper and lower surfaces thereof; a first dielectric layer formed on the first conductive layer; and a second conductive layer formed on the first dielectric layer.Type: ApplicationFiled: October 23, 2019Publication date: April 30, 2020Inventors: Jong Min YOOK, Jun Chul KIM, Dong Su KIM
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Publication number: 20200091028Abstract: Disclosed is a semiconductor package. The semiconductor package includes a semiconductor chip on which an electrode pad is disposed, at least one input/output segment disposed around a side surface of the semiconductor chip to be spaced apart from the semiconductor chip and transmitting an electric signal, and an insulating layer filled between the semiconductor chip and the input/output segment. The insulating layer is provided on the semiconductor chip and the input/output segment to fix and insulate the semiconductor chip and the input/output segment from each other. The semiconductor further includes an electrode pattern provided on the insulating layer and configured to electrically connect the electrode pad of the semiconductor chip and the input/output segment.Type: ApplicationFiled: November 8, 2018Publication date: March 19, 2020Inventors: Jong Min YOOK, Jun Chul KIM, Dong Su KIM
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Patent number: 10559506Abstract: A method of inspecting a semiconductor device including setting a target place on a wafer, the target place including a deep trench, forming a first cut surface by performing first milling on the target place in a first direction, obtaining first image data of the first cut surface, forming a second cut surface by performing second milling on the target place in a second direction opposite to the first direction, obtaining second image data of the second cut surface, obtaining a plurality of first critical dimension (CD) values for the deep trench from the first image data, obtaining a plurality of second CD values for the deep trench from the second image data, analyzing a degree of bending of the deep trench based on the first CD values and the second CD values, and providing the semiconductor device meeting a condition based on results of the analyzing may be provided.Type: GrantFiled: August 27, 2018Date of Patent: February 11, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Min Kook Kim, Jun Chul Kim, Myung Suk Um, Yu Sin Yang, Ye Ny Yim
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Publication number: 20190198404Abstract: A method of inspecting a semiconductor device including setting a target place on a wafer, the target place including a deep trench, forming a first cut surface by performing first milling on the target place in a first direction, obtaining first image data of the first cut surface, forming a second cut surface by performing second milling on the target place in a second direction opposite to the first direction, obtaining second image data of the second cut surface, obtaining a plurality of first critical dimension (CD) values for the deep trench from the first image data, obtaining a plurality of second CD values for the deep trench from the second image data, analyzing a degree of bending of the deep trench based on the first CD values and the second CD values, and providing the semiconductor device meeting a condition based on results of the analyzing may be provided.Type: ApplicationFiled: August 27, 2018Publication date: June 27, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Min Kook KIM, Jun Chul KIM, Myung Suk UM, Yu Sin YANG, Ye Ny YIM
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Publication number: 20190198413Abstract: The present invention provides a semiconductor package and a manufacturing method thereof, the semiconductor package including: at least one semiconductor chip; a molding layer surrounding the semiconductor chip; a redistribution layer provided on a first surface of the molding layer to transmit an electrical signal; and at least one connecting element transmitting an electrical signal from the first surface of the molding layer to a second surface of the molding layer. According to the present invention, since the connecting element, which is an independent element capable of transmitting an electrical signal in a vertical direction of the semiconductor package, is included in the molding layer, it is possible to integrate an electric element such as an antenna into a rear surface space of the semiconductor package.Type: ApplicationFiled: December 19, 2018Publication date: June 27, 2019Inventors: Jong Min YOOK, Jun Chul KIM, Dong Su KIM
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Patent number: D1062525Type: GrantFiled: June 22, 2022Date of Patent: February 18, 2025Assignee: YKK CORPORATIONInventors: Naoki Kasuya, Yong Chul Lee, Kyong Ah Kim, Jun Won Lee