Patents by Inventor Jun-Chul Kim

Jun-Chul Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250072019
    Abstract: Disclosed herein are a Schottky barrier diode (SBD) and a method of manufacturing the same. The SBD includes a substrate, an ohmic layer formed on a portion of an upper portion of the substrate, a Schottky layer formed on a portion of an upper portion of the ohmic layer, an insulating layer formed on a portion of the upper portion of the ohmic layer, a low-k material layer formed on a portion of the upper portion of the substrate, and a Schottky metal layer formed on portions of upper portions of the low-k material layer and the insulating layer.
    Type: Application
    Filed: July 11, 2024
    Publication date: February 27, 2025
    Inventors: Jun Hwan SHIN, Young Ho Kim, Eui Su Lee, Jin Chul Cho, Soo Cheol Kang, Dong Woo Park, II Min Lee
  • Publication number: 20250062238
    Abstract: A semiconductor package is provided. The semiconductor package comprises a package substrate, a first semiconductor chip on the package substrate, a second semiconductor chip spaced apart from the first semiconductor chip on the package substrate, and a bridge die placed below the first semiconductor chip and the second semiconductor chip on the package substrate, wherein the bridge die includes a first face that faces the first semiconductor chip and the second semiconductor chip, a second face that faces the package substrate, a connection wiring structure which is placed on the first face, and connects the first semiconductor chip and the second semiconductor chip, and a power wiring structure which is placed on the second face, and provides power to the first semiconductor chip and the second semiconductor chip.
    Type: Application
    Filed: February 26, 2024
    Publication date: February 20, 2025
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Bong Wee YU, Chang Soo KIM, Byung Chul JEON, Jun Ho HUH
  • Patent number: 12230816
    Abstract: A secondary battery case includes a recess part recessed downward, and a sealing part provided around the recess part when the secondary battery case is unfolded. At least portions of the sealing part are attached to each other to seal inner surfaces of the recess part from an outside. A secondary battery includes an electrode assembly and the secondary battery case. The recess part of the secondary battery case has a width that corresponds to a thickness of the electrode assembly.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: February 18, 2025
    Assignee: LG Energy Solution, Ltd.
    Inventors: Hyun Beom Kim, Jun Kyu Park, Jeong Min Ha, Gi Man Kim, Hyun Chul Ha
  • Publication number: 20250056993
    Abstract: A display device includes a substrate including sub-pixel circuit areas that are arranged in m rows and n columns, where m and n are positive integers, first gate lines extending in a row direction, data lines extending in a column direction, initialization power lines extending in the row direction, including first power lines disposed in sub-pixel circuit areas of odd rows and receiving a first initialization voltage and second power lines disposed in sub-pixel circuit areas of even rows and receiving a second initialization voltage, and transmission lines extending in the column direction, including first transmission lines disposed in sub-pixel circuit areas of odd columns and receiving the first initialization voltage from the first power lines and second transmission lines disposed in sub-pixel circuit areas of even columns and receiving the second initialization voltage from the second power lines.
    Type: Application
    Filed: October 21, 2024
    Publication date: February 13, 2025
    Inventors: JUN-YONG AN, MIN JEONG KIM, HYUNGJUN PARK, NUREE UM, KWANG-CHUL JUNG
  • Patent number: 12209149
    Abstract: A continuous preparation system of a conjugated diene-based polymer having improved rolling resistance properties is provided. By utilizing the continuous preparation system a polymerization conversion ratio at an initial stage of polymerization is easy to control, long time operation is possible and productivity is excellent.
    Type: Grant
    Filed: December 24, 2020
    Date of Patent: January 28, 2025
    Assignee: LG Chem, Ltd.
    Inventors: Tae Chul Lee, Su Hwa Kim, No Ma Kim, Jun Seok Ko
  • Patent number: 12014881
    Abstract: The present invention provides a method for manufacturing a high frequency capacitor, including preparing a substrate for formation of the capacitor, forming a dielectric layer at an upper surface of the substrate, forming an upper electrode at an upper surface of the dielectric layer, and removing a portion of a lower surface of the substrate, to expose a lower surface of the dielectric layer, and forming a lower electrode at the lower surface of the dielectric layer. The high frequency capacitor includes a dielectric layer having a uniform surface, a thick upper electrode, and a thick lower electrode and, as such, exhibits high quality factor (Q) even at a high frequency.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: June 18, 2024
    Assignee: KOREA ELECTRONICS TECHNOLOGY INSTITUTE
    Inventors: Jong Min Yook, Je In Yu, Jun Chul Kim, Dong Su Kim
  • Patent number: 11658374
    Abstract: A quasi-coaxial transmission line, a semiconductor package including the same and a method of manufacturing the same are disclosed. The quasi-coaxial transmission line includes a core, which is formed through an upper surface and a lower surface of a base substrate so as to transmit an electrical signal, and a shield, which is spaced apart from the core and which coaxially surrounds a side surface of the core, at least a portion of the shield being removed so as to form an open portion. The quasi-coaxial transmission line is capable of preventing distortion of an electrical signal at a portion thereof that is connected to an external circuit board and to reduce an area of a semiconductor package including the quasi-coaxial transmission line.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: May 23, 2023
    Assignee: KOREA ELECTRONICS TECHNOLOGY INSTITUTE
    Inventors: Jong Min Yook, Jun Chul Kim, Dong Su Kim
  • Patent number: 11538770
    Abstract: A semiconductor package includes a semiconductor chip including an electrode pad formed on the top surface thereof, a passive device embedded in the semiconductor package, the passive device having no functional electrode on the top surface thereof, a cover layer covering the semiconductor chip and the passive device, and at least one electrode pattern formed on the cover layer to transmit electrical signals. The cover layer includes at least one first opening formed to expose a region in which the functional electrode is to be formed. The electrode pattern includes a functional electrode portion formed in a region in which the functional electrode of the passive device is to be formed through the first opening. In the process of forming the electrode pattern, a functional electrode of the passive device is formed together therewith, thereby eliminating a separate step of manufacturing a functional electrode and thus reducing manufacturing costs.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: December 27, 2022
    Assignee: Korea Electronics Technology Institute
    Inventors: Jong Min Yook, Jun Chul Kim, Dong Su Kim
  • Publication number: 20220328253
    Abstract: The present invention provides a method for manufacturing a high frequency capacitor, including preparing a substrate for formation of the capacitor, forming a dielectric layer at an upper surface of the substrate, forming an upper electrode at an upper surface of the dielectric layer, and removing a portion of a lower surface of the substrate, to expose a lower surface of the dielectric layer, and forming a lower electrode at the lower surface of the dielectric layer. The high frequency capacitor includes a dielectric layer having a uniform surface, a thick upper electrode, and a thick lower electrode and, as such, exhibits high quality factor (Q) even at a high frequency.
    Type: Application
    Filed: March 30, 2022
    Publication date: October 13, 2022
    Inventors: Jong Min YOOK, Je In YU, Jun Chul KIM, Dong Su KIM
  • Patent number: 11197372
    Abstract: An embodiment of the present invention provides a capacitor having a through hole structure and a manufacturing method therefor. The capacitor having the through hole structure includes: a baseboard having a through hole penetrating from an upper surface of the baseboard to a lower surface thereof; a first conductive layer formed on an internal surface of the through hole, and the upper surface of the baseboard, the lower surface thereof, or both the upper and lower surfaces thereof; a first dielectric layer formed on the first conductive layer; and a second conductive layer formed on the first dielectric layer.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: December 7, 2021
    Assignee: KOREA ELECTRONICS TECHNOLOGY INSTITUTE
    Inventors: Jong Min Yook, Jun Chul Kim, Dong Su Kim
  • Publication number: 20200381797
    Abstract: A quasi-coaxial transmission line, a semiconductor package including the same and a method of manufacturing the same are disclosed. The quasi-coaxial transmission line includes a core, which is formed through an upper surface and a lower surface of a base substrate so as to transmit an electrical signal, and a shield, which is spaced apart from the core and which coaxially surrounds a side surface of the core, at least a portion of the shield being removed so as to form an open portion. The quasi-coaxial transmission line is capable of preventing distortion of an electrical signal at a portion thereof that is connected to an external circuit board and to reduce an area of a semiconductor package including the quasi-coaxial transmission line.
    Type: Application
    Filed: May 12, 2020
    Publication date: December 3, 2020
    Inventors: Jong Min YOOK, Jun Chul KIM, Dong Su KIM
  • Publication number: 20200373256
    Abstract: A semiconductor package includes a semiconductor chip including an electrode pad formed on the top surface thereof, a passive device embedded in the semiconductor package, the passive device having no functional electrode on the top surface thereof, a cover layer covering the semiconductor chip and the passive device, and at least one electrode pattern formed on the cover layer to transmit electrical signals. The cover layer includes at least one first opening formed to expose a region in which the functional electrode is to be formed. The electrode pattern includes a functional electrode portion formed in a region in which the functional electrode of the passive device is to be formed through the first opening. In the process of forming the electrode pattern, a functional electrode of the passive device is formed together therewith, thereby eliminating a separate step of manufacturing a functional electrode and thus reducing manufacturing costs.
    Type: Application
    Filed: May 20, 2020
    Publication date: November 26, 2020
    Applicant: Korea Electronics Technology Institute
    Inventors: Jong Min YOOK, Jun Chul KIM, Dong Su KIM
  • Publication number: 20200137889
    Abstract: An embodiment of the present invention provides a capacitor having a through hole structure and a manufacturing method therefor. The capacitor having the through hole structure includes: a baseboard having a through hole penetrating from an upper surface of the baseboard to a lower surface thereof; a first conductive layer formed on an internal surface of the through hole, and the upper surface of the baseboard, the lower surface thereof, or both the upper and lower surfaces thereof; a first dielectric layer formed on the first conductive layer; and a second conductive layer formed on the first dielectric layer.
    Type: Application
    Filed: October 23, 2019
    Publication date: April 30, 2020
    Inventors: Jong Min YOOK, Jun Chul KIM, Dong Su KIM
  • Publication number: 20200091028
    Abstract: Disclosed is a semiconductor package. The semiconductor package includes a semiconductor chip on which an electrode pad is disposed, at least one input/output segment disposed around a side surface of the semiconductor chip to be spaced apart from the semiconductor chip and transmitting an electric signal, and an insulating layer filled between the semiconductor chip and the input/output segment. The insulating layer is provided on the semiconductor chip and the input/output segment to fix and insulate the semiconductor chip and the input/output segment from each other. The semiconductor further includes an electrode pattern provided on the insulating layer and configured to electrically connect the electrode pad of the semiconductor chip and the input/output segment.
    Type: Application
    Filed: November 8, 2018
    Publication date: March 19, 2020
    Inventors: Jong Min YOOK, Jun Chul KIM, Dong Su KIM
  • Patent number: 10559506
    Abstract: A method of inspecting a semiconductor device including setting a target place on a wafer, the target place including a deep trench, forming a first cut surface by performing first milling on the target place in a first direction, obtaining first image data of the first cut surface, forming a second cut surface by performing second milling on the target place in a second direction opposite to the first direction, obtaining second image data of the second cut surface, obtaining a plurality of first critical dimension (CD) values for the deep trench from the first image data, obtaining a plurality of second CD values for the deep trench from the second image data, analyzing a degree of bending of the deep trench based on the first CD values and the second CD values, and providing the semiconductor device meeting a condition based on results of the analyzing may be provided.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: February 11, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min Kook Kim, Jun Chul Kim, Myung Suk Um, Yu Sin Yang, Ye Ny Yim
  • Publication number: 20190198404
    Abstract: A method of inspecting a semiconductor device including setting a target place on a wafer, the target place including a deep trench, forming a first cut surface by performing first milling on the target place in a first direction, obtaining first image data of the first cut surface, forming a second cut surface by performing second milling on the target place in a second direction opposite to the first direction, obtaining second image data of the second cut surface, obtaining a plurality of first critical dimension (CD) values for the deep trench from the first image data, obtaining a plurality of second CD values for the deep trench from the second image data, analyzing a degree of bending of the deep trench based on the first CD values and the second CD values, and providing the semiconductor device meeting a condition based on results of the analyzing may be provided.
    Type: Application
    Filed: August 27, 2018
    Publication date: June 27, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Min Kook KIM, Jun Chul KIM, Myung Suk UM, Yu Sin YANG, Ye Ny YIM
  • Publication number: 20190198413
    Abstract: The present invention provides a semiconductor package and a manufacturing method thereof, the semiconductor package including: at least one semiconductor chip; a molding layer surrounding the semiconductor chip; a redistribution layer provided on a first surface of the molding layer to transmit an electrical signal; and at least one connecting element transmitting an electrical signal from the first surface of the molding layer to a second surface of the molding layer. According to the present invention, since the connecting element, which is an independent element capable of transmitting an electrical signal in a vertical direction of the semiconductor package, is included in the molding layer, it is possible to integrate an electric element such as an antenna into a rear surface space of the semiconductor package.
    Type: Application
    Filed: December 19, 2018
    Publication date: June 27, 2019
    Inventors: Jong Min YOOK, Jun Chul KIM, Dong Su KIM
  • Patent number: 10170538
    Abstract: In one embodiment of the present invention, there is provided an MIS capacitor, including: a lower electrode formed with a semiconductor substrate having electrical conductivity and through which an electrical signal passes at a lower surface thereof; an insulating layer formed on the lower electrode; an upper electrode formed on the insulating layer and through which the electrical signal passes at an upper surface thereof; and a first conductive layer formed on side surfaces of the lower electrode so that the electrical signal passing the lower surface and an upper surface of the lower electrode passes along the side surfaces of the lower electrode, wherein the first conductive layer has electro conductivity higher than the electro conductivity of the lower electrode.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: January 1, 2019
    Assignee: Korea Electronics Technology Institute
    Inventors: Jun Chul Kim, Dong Su Kim, Jong Min Yook
  • Publication number: 20180182842
    Abstract: In one embodiment of the present invention, there is provided an MIS capacitor, including: a lower electrode formed with a semiconductor substrate having electrical conductivity and through which an electrical signal passes at a lower surface thereof; an insulating layer formed on the lower electrode; an upper electrode formed on the insulating layer and through which the electrical signal passes at an upper surface thereof; and a first conductive layer formed on side surfaces of the lower electrode so that the electrical signal passing the lower surface and an upper surface of the lower electrode passes along the side surfaces of the lower electrode, wherein the first conductive layer has electro conductivity higher than the electro conductivity of the lower electrode.
    Type: Application
    Filed: November 27, 2017
    Publication date: June 28, 2018
    Applicant: KOREA ELECTRONICS TECHNOLOGY INSTITUTE
    Inventors: Jun Chul Kim, Dong Su Kim, Jong Min Yook
  • Patent number: D1062525
    Type: Grant
    Filed: June 22, 2022
    Date of Patent: February 18, 2025
    Assignee: YKK CORPORATION
    Inventors: Naoki Kasuya, Yong Chul Lee, Kyong Ah Kim, Jun Won Lee