Patents by Inventor Jun-De JIN

Jun-De JIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250169085
    Abstract: Semiconductor device isolation is provided. In one aspect, a semiconductor device include a spiral inductor. The semiconductor device includes a patterned ground shield (PGS) electrically coupled with the spiral inductor. The semiconductor device includes a filter configured to exchange energy with the PGS. The semiconductor device includes a circuit vertically spaced from the inductor, the PGS disposed between the circuit and the spiral inductor.
    Type: Application
    Filed: November 20, 2023
    Publication date: May 22, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Chun Chang, Hsieh-Hung Hsieh, Tzu-Jin Yeh, Jun-De Jin, Ching-Chung Hsu, Chung-Long Chang, Hua-Chou Tseng
  • Patent number: 12237863
    Abstract: Disclosed is a RF switch module and methods to fabricate and operate such RF switch to alternatively couple an antenna to either a transmitter transmission line or a receiver transmission line to realize lower distortion of a signal at high frequencies with improved insertion loss and without affecting isolation. In one embodiment, a Radio Frequency (RF) switch module, includes, a switch circuit for switching between transmitting first signals from a transmitter unit to an antenna and transmitting second signals from the antenna to the receiver unit, wherein the switch circuit comprises a plurality of field effect transistors (FETs), wherein each of the plurality of FETs comprises stacked gate dielectrics and at least three metal contacts to a conductive gate, wherein the stacked gate dielectrics comprises at least one first dielectric layer, wherein the first dielectric layer comprises a negative-capacitance material.
    Type: Grant
    Filed: August 8, 2023
    Date of Patent: February 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jun-De Jin
  • Publication number: 20240395740
    Abstract: Devices and methods for enhancing insertion loss performance of an antenna switch are disclosed. In one example, a semiconductor device formed to serve as an antenna switch is disclosed. The semiconductor device includes: a substrate, a dielectric layer and a polysilicon region. The substrate includes: an intrinsic substrate; a metal-oxide-semiconductor device extending into the intrinsic substrate; and at least one isolation feature extending into and in contact with the intrinsic substrate. The at least one isolation feature is disposed adjacent to the metal-oxide-semiconductor device.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Inventor: Jun-De JIN
  • Patent number: 12142585
    Abstract: Devices and methods for enhancing insertion loss performance of an antenna switch are disclosed. In one example, a semiconductor device formed to serve as an antenna switch is disclosed. The semiconductor device includes: a substrate, a dielectric layer and a polysilicon region. The substrate includes: an intrinsic substrate; a metal-oxide-semiconductor device extending into the intrinsic substrate; and at least one isolation feature extending into and in contact with the intrinsic substrate. The at least one isolation feature is disposed adjacent to the metal-oxide-semiconductor device.
    Type: Grant
    Filed: November 7, 2023
    Date of Patent: November 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jun-De Jin
  • Publication number: 20240371859
    Abstract: A semiconductor device includes a substrate, a first metal-oxide-semiconductor device and a at least one first resistor. The substrate includes a non-doped region. The first metal-oxide-semiconductor device extends into the substrate. The first metal-oxide-semiconductor device is adjacent to the non-doped region. The at least one first resistor is disposed right above the non-doped region and arranged in a first row aligned with the first metal-oxide-semiconductor device in a first direction.
    Type: Application
    Filed: July 15, 2024
    Publication date: November 7, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jun-De JIN, Tzu-Jin YEH
  • Publication number: 20240312982
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a transistor, at least one isolation and at least one non-doped region. The substrate includes a lower portion. The transistor is disposed on the lower portion. The at least one isolation is adjacent to the transistor, and disposed on the lower portion. The at least one non-doped region is disposed between and adjacent to the isolation and the lower portion.
    Type: Application
    Filed: May 20, 2024
    Publication date: September 19, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jun-De JIN, Tzu-Jin YEH
  • Patent number: 12080706
    Abstract: A semiconductor device includes a substrate, a first metal-oxide-semiconductor device and a at least one first resistor. The substrate includes a non-doped region. The first metal-oxide-semiconductor device extends into the substrate. The first metal-oxide-semiconductor device is adjacent to the non-doped region. The at least one first resistor is disposed right above the non-doped region and arranged in a first row aligned with the first metal-oxide-semiconductor device in a first direction.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: September 3, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jun-De Jin, Tzu-Jin Yeh
  • Patent number: 12021078
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate, a transistor, at least one isolation and at least one non-doped region. The substrate includes a lower portion. The transistor is disposed on the lower portion. The at least one isolation is adjacent to the transistor, and disposed on the lower portion. The at least one non-doped region is disposed between and adjacent to the isolation and the lower portion.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: June 25, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jun-De Jin, Tzu-Jin Yeh
  • Publication number: 20240145587
    Abstract: A gallium nitride-on-silicon structure is disclosed in which the two-dimensional electron gas (2DEG) layer is a discontinuous layer that includes at least two 2DEG segments. Each 2DEG segment is separated from another 2DEG segment by a gap. The 2DEG layer can be depleted by a p-doped gallium nitride layer that is disposed over a portion of an aluminum gallium nitride layer. Additionally or alternatively, a trench may be formed in the structure through the 2DEG layer to produce a gap in the 2DEG layer. An electrical component is positioned over at least a portion of a gap.
    Type: Application
    Filed: January 9, 2024
    Publication date: May 2, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jun-De Jin, Chan-Hong Chern
  • Publication number: 20240071961
    Abstract: Devices and methods for enhancing insertion loss performance of an antenna switch are disclosed. In one example, a semiconductor device formed to serve as an antenna switch is disclosed. The semiconductor device includes: a substrate, a dielectric layer and a polysilicon region. The substrate includes: an intrinsic substrate; a metal-oxide-semiconductor device extending into the intrinsic substrate; and at least one isolation feature extending into and in contact with the intrinsic substrate. The at least one isolation feature is disposed adjacent to the metal-oxide-semiconductor device.
    Type: Application
    Filed: November 7, 2023
    Publication date: February 29, 2024
    Inventor: Jun-De JIN
  • Patent number: 11888055
    Abstract: A gallium nitride-on-silicon structure is disclosed in which the two-dimensional electron gas (2DEG) layer is a discontinuous layer that includes at least two 2DEG segments. Each 2DEG segment is separated from another 2DEG segment by a gap. The 2DEG layer can be depleted by a p-doped gallium nitride layer that is disposed over a portion of an aluminum gallium nitride layer. Additionally or alternatively, a trench may be formed in the structure through the 2DEG layer to produce a gap in the 2DEG layer. An electrical component is positioned over at least a portion of a gap.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: January 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jun-De Jin, Chan-Hong Chern
  • Patent number: 11855012
    Abstract: Devices and methods for enhancing insertion loss performance of an antenna switch are disclosed. In one example, a semiconductor device formed to serve as an antenna switch is disclosed. The semiconductor device includes: a substrate, a dielectric layer and a polysilicon region. The substrate includes: an intrinsic substrate; a metal-oxide-semiconductor device extending into the intrinsic substrate; and at least one isolation feature extending into and in contact with the intrinsic substrate. The at least one isolation feature is disposed adjacent to the metal-oxide-semiconductor device.
    Type: Grant
    Filed: April 5, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jun-De Jin
  • Publication number: 20230387960
    Abstract: Disclosed is a RF switch module and methods to fabricate and operate such RF switch to alternatively couple an antenna to either a transmitter transmission line or a receiver transmission line to realize lower distortion of a signal at high frequencies with improved insertion loss and without affecting isolation. In one embodiment, a Radio Frequency (RF) switch module, includes, a switch circuit for switching between transmitting first signals from a transmitter unit to an antenna and transmitting second signals from the antenna to the receiver unit, wherein the switch circuit comprises a plurality of field effect transistors (FETs), wherein each of the plurality of FETs comprises stacked gate dielectrics and at least three metal contacts to a conductive gate, wherein the stacked gate dielectrics comprises at least one first dielectric layer, wherein the first dielectric layer comprises a negative-capacitance material.
    Type: Application
    Filed: August 8, 2023
    Publication date: November 30, 2023
    Inventor: Jun-De JIN
  • Patent number: 11824249
    Abstract: A coplanar waveguide structure includes a dielectric layer disposed over at least a portion of a substrate and a planar transmission line disposed within the dielectric layer. In some instances, the planar transmission line can include a conductive signal line and one or more ground lines. In other instances, the planar transmission line may include a conductive stacked signal line and one or more stacked ground lines.
    Type: Grant
    Filed: November 23, 2022
    Date of Patent: November 21, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jun-De Jin
  • Patent number: 11804869
    Abstract: Disclosed is a RF switch module and methods to fabricate and operate such RF switch to alternatively couple an antenna to either a transmitter transmission line or a receiver transmission line to realize lower distortion of a signal at high frequencies with improved insertion loss and without affecting isolation. In one embodiment, a Radio Frequency (RF) switch module, includes, a switch circuit for switching between transmitting first signals from a transmitter unit to an antenna and transmitting second signals from the antenna to the receiver unit, wherein the switch circuit comprises a plurality of field effect transistors (FETs), wherein each of the plurality of FETs comprises stacked gate dielectrics and at least three metal contacts to a conductive gate, wherein the stacked gate dielectrics comprises at least one first dielectric layer, wherein the first dielectric layer comprises a negative-capacitance material.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: October 31, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jun-De Jin
  • Publication number: 20230089282
    Abstract: A coplanar waveguide structure includes a dielectric layer disposed over at least a portion of a substrate and a planar transmission line disposed within the dielectric layer. In some instances, the planar transmission line can include a conductive signal line and one or more ground lines. In other instances, the planar transmission line may include a conductive stacked signal line and one or more stacked ground lines.
    Type: Application
    Filed: November 23, 2022
    Publication date: March 23, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jun-De Jin
  • Publication number: 20230030906
    Abstract: A resonator device includes a substrate with a first number of fins extending over the substrate. The fins extend along the substrate in a first direction. A second number of conductive fingers are provided over the fins, which extend in a second direction perpendicular to the first direction. The first number is less than or equal to the second number. The conductive fingers are configured to receive an input signal such that the conductive fingers resonate at an output frequency. The conductive fingers define a finger pitch therebetween, and the output frequency is based on the finger pitch.
    Type: Application
    Filed: January 27, 2022
    Publication date: February 2, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jun-De Jin
  • Patent number: 11515609
    Abstract: A coplanar waveguide structure includes a dielectric layer disposed over at least a portion of a substrate and a planar transmission line disposed within the dielectric layer. In some instances, the planar transmission line can include a conductive signal line and one or more ground lines. In other instances, the planar transmission line may include a conductive stacked signal line and one or more stacked ground lines.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: November 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Jun-De Jin
  • Publication number: 20220336446
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate, a transistor, at least one isolation and at least one non-doped region. The substrate includes a lower portion. The transistor is disposed on the lower portion. The at least one isolation is adjacent to the transistor, and disposed on the lower portion. The at least one non-doped region is disposed between and adjacent to the isolation and the lower portion.
    Type: Application
    Filed: June 29, 2022
    Publication date: October 20, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jun-De JIN, Tzu-Jin YEH
  • Publication number: 20220328473
    Abstract: A semiconductor device includes a substrate, a first metal-oxide-semiconductor device and a at least one first resistor. The substrate includes a non-doped region. The first metal-oxide-semiconductor device extends into the substrate. The first metal-oxide-semiconductor device is adjacent to the non-doped region. The at least one first resistor is disposed right above the non-doped region and arranged in a first row aligned with the first metal-oxide-semiconductor device in a first direction.
    Type: Application
    Filed: June 29, 2022
    Publication date: October 13, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jun-De JIN, Tzu-Jin YEH