Abstract: To provide a method for predicting a soybean yield at an early stage with high accuracy. The method for predicting a soybean yield comprises: acquiring analytical data of one or more components from a leaf sample collected from the soybean; and predicting a soybean yield using a correlation between the data and a soybean yield.

Abstract: Provided is a method with which an ?-allylated cycloalkanone is obtained from a cyclic compound cycloalkanone used as a starting material. The method is a method for producing an ?-allylated cycloalkanone represented by General Formula (III), and the method includes: a step 1: reacting a compound represented by General Formula (I) and alcohol having 1 or more and 4 or less of carbon atoms in the presence of a first acid catalyst and optionally a dehydrating agent; and a step 2: reacting a crude product obtained in the step 1 and a compound represented by General Formula (II) in the presence of a second acid catalyst to produce an ?-allylated cycloalkanone represented by General Formula (III). The step 1 and the step 2 are consecutively performed.

Abstract: Provided is a method with which an ?-allylated cycloalkanone is obtained from a macroyclic compound used as a starting material. The method is a method for producing an ?-allylated cycloalkanone represented by General Formula (IV), and the method includes a step of reacting a compound represented by General Formula (I) and/or a compound represented by General Formula (II) with a compound represented by General Formula (III) in the presence of an acid catalyst to produce an ?-allylated cycloalkanone represented by General Formula (IV), the acid catalyst including an acid catalyst that includes an ammonium cation and an anion.

Abstract: A memory system includes first, second, third, and fourth nonvolatile memory, a memory controller configured to modulate write data for the first and second memory into a first time slot of a data signal according to an allocation scheme, and modulate write data for the third and fourth memory into a second time slot of the data signal according to the allocation scheme, a first bridge circuit configured according to the allocation scheme to extract first write data from the first time slot, a second bridge circuit configured according to the allocation scheme to extract second write data from the first time slot, a third bridge circuit configured according to the allocation scheme to extract third write data from the second time slot, and a fourth bridge circuit configured according to the allocation scheme to extract fourth write data from the second time slot.

Abstract: According to one embodiment, a processor is configured to calculate a calculation amount in inference time of a neural network, using a result of summing, with respect to a group to which quantization is applied, products of the number of product-sum operations and bit widths of weight for the product-sum operations in the neural network. Then, the processor is configured to optimize a value of the weight and a quantization step size to minimize the recognition error by the neural network based on the calculated calculation amount, and execute computing about the neural network based on the optimized weight and the quantization step size.

Abstract: According to one embodiment, in a processing circuit of a computation system, a plurality of comparators corresponds to the respective columns, each including a first input node, a second input node, and an output node, the first input node receiving any one of the second signals, the second input node receiving a signal corresponding to a global reference signal provided to each second input node, the output node outputting a local signal. A global circuit is provided common to the plurality of comparators, the global circuit generating a global signal according to a plurality of the local signals, the global circuit generating the global reference signal by an SAR method according to the global signal. The processing circuit disables some of the plurality of comparators according to the local signals and the global signal.

Abstract: According to an embodiment, an arithmetic device configured to execute an operation related to a neural network approximately calculates similarities between a first vector and a plurality of second vectors. Further, the arithmetic device selects, among the plurality of second vectors, a plurality of third vectors whose similarities are equal to or greater than a threshold. Furthermore, the arithmetic device also calculates similarities between the first vector and the selected plurality of third vectors.

Abstract: According to one embodiment, a training device includes a first memory, a second memory, and a processing circuit. The first memory is a memory accessible at a higher speed than the second memory. The training device executes a training process of a machine learning model using a stochastic gradient descent method. The processing circuit stores a first output produced by the process of a first layer in the second memory, and stores a second output produced by the process of a second layer, in a forward process of the training process. The processing circuit updates a parameter of the second layer based on the second output stored in the first memory, reads the first output stored in the second memory, and updates a parameter of the first layer based on the read first output, in a backward process of the training process.

Abstract: According to an embodiment, a quantum annealing apparatus includes: an output unit acquiring and outputting components in a Z axis from a plurality of quantum bits in a quantum calculation; and an operation unit executes: a selecting process of selecting a first quantum bit, a second quantum bit and a third quantum bit, the second quantum bit and the third quantum bit being coupled in the quantum calculation unit; a first rotating operation of rotating each of the second quantum bit and the third quantum bit by 90° around a first axis perpendicular to the Z axis; an interaction operation of causing the first quantum bit and the second quantum bit to interact with each other; and a second rotating operation of rotating each of the second quantum bit and the third quantum bit by 90° around a second axis perpendicular to the Z axis and the first axis.

Abstract: A memory system includes first, second, third, and fourth nonvolatile memory, a memory controller configured to modulate write data for the first and second memory into a first time slot of a data signal according to an allocation scheme, and modulate write data for the third and fourth memory into a second time slot of the data signal according to the allocation scheme, a first bridge circuit configured according to the allocation scheme to extract first write data from the first time slot, a second bridge circuit configured according to the allocation scheme to extract second write data from the first time slot, a third bridge circuit configured according to the allocation scheme to extract third write data from the second time slot, and a fourth bridge circuit configured according to the allocation scheme to extract fourth write data from the second time slot.

Abstract: According to one embodiment, a semiconductor memory device includes a memory, a controller, and a sense amplifier. The memory includes a plurality of memory cells, wherein each of the memory cells can store a multi level indicating one data. The controller writes the multi level to one cell of the memory. The sense amplifier performs unary read of data from the multi level written in the one cell. The data is data in which an error of a predetermined lower significant bit is allowed. The controller reads data indicated by the multi level stored in the one cell of the memory from the sense amplifier.

Abstract: A memory system includes first, second, third, and fourth nonvolatile memory, a memory controller configured to modulate write data for the first and second memory into a first time slot of a data signal according to an allocation scheme, and modulate write data for the third and fourth memory into a second time slot of the data signal according to the allocation scheme, a first bridge circuit configured according to the allocation scheme to extract first write data from the first time slot, a second bridge circuit configured according to the allocation scheme to extract second write data from the first time slot, a third bridge circuit configured according to the allocation scheme to extract third write data from the second time slot, and a fourth bridge circuit configured according to the allocation scheme to extract fourth write data from the second time slot.

Abstract: According to one embodiment, a semiconductor memory device includes a memory, a controller, and a sense amplifier. The memory includes a plurality of memory cells, wherein each of the memory cells can store a multi level indicating one data. The controller writes the multi level to one cell of the memory. The sense amplifier performs unary read of data from the multi level written in the one cell. The data is data in which an error of a predetermined lower significant bit is allowed. The controller reads data indicated by the multi level stored in the one cell of the memory from the sense amplifier.

Abstract: According to one embodiment, in a reception apparatus, a reception node is capable of being connected to a wired communication channel. A first frequency conversion circuit is electrically connected to the reception node. A second frequency conversion circuit is electrically connected to the reception node. A first adder circuit is electrically connected to the first frequency conversion circuit. A second adder circuit is electrically connected to the second frequency conversion circuit. A first correction circuit is electrically connected between the first frequency conversion circuit and the second adder circuit. A second correction circuit is electrically connected between the second frequency conversion circuit and the first adder circuit. The first correction circuit includes a reverse phase amplifier and a first capacitative element. The second correction circuit includes a positive phase amplifier and a second capacitative element.

Abstract: According to an embodiment, a quantum annealing apparatus includes: an output unit acquiring and outputting components in a Z axis from a plurality of quantum bits in a quantum calculation; and an operation unit executes: a selecting process of selecting a first quantum bit, a second quantum bit and a third quantum bit, the second quantum bit and the third quantum bit being coupled in the quantum calculation unit; a first rotating operation of rotating each of the second quantum bit and the third quantum bit by 90° around a first axis perpendicular to the Z axis; an interaction operation of causing the first quantum bit and the second quantum bit to interact with each other; and a second rotating operation of rotating each of the second quantum bit and the third quantum bit by 90° around a second axis perpendicular to the Z axis and the first axis.

Abstract: It is intended to provide a component promoting the growth of leguminous plants. The present invention provides a promoter for leguminous plant growth comprising a glycoside of soyasapogenol B as an active ingredient, and a method for promoting the growth of a leguminous plant using a glycoside of soyasapogenol B as an active ingredient. The glycoside of soyasapogenol B is a glycoside having a hydroxy group at position C-22 of the soyasapogenol B and having a saccharide bonded to a hydroxy group at position C-3 of the soyasapogenol B.

Abstract: According to one embodiment, a transmitter includes a 1st circuit configured to execute a 1st band limitation by waveform shaping in a time region with respect to 1st data relating to a 1st channel to generate a 1st signal; a 2nd circuit configured to execute a 2nd band limitation by the waveform shaping in the time region with respect to 2nd data relating to a 2nd channel to generate a 2nd signal; a 3rd circuit configured to generate a 3rd signal based on the 1st signal and a 1st frequency relating to the 1st channel; a 4th circuit configured to generate a 4th signal based on the 2nd signal and a 2nd frequency relating to the 2nd channel; and a 5th circuit configured to generate a 5th signal by multiplexing the 3rd signal and the 4th signal.

Abstract: According to one embodiment, an information processing apparatus for convolution operations in layers of a convolutional neural network, includes a memory and a product-sum operating circuitry. The memory is configured to store items of information indicative of an input, a weight to the input, and a bit width determined for each filter of the weight. The product-sum operating circuitry is configured to perform a product-sum operation based on the items of information indicative of the input, the weight, and the bit width, stored in the memory.

Abstract: A memcapacitor according to an embodiment includes a first electrode, a first dielectric layer provided on the first electrode, a plurality of variable resistance portions provided separately from each other on the first dielectric layer, a second dielectric layer provided on the first dielectric layer and between the variable resistance portions, and a second electrode provided on the variable resistance portions and the second dielectric layer. Each of the variable resistance portions is formed of a material that allows diffusion of metal atoms constituting the second electrode to inside of the variable resistance portion, and the second dielectric layer is formed of a material that prevents diffusion of the metal atoms constituting the second electrode to inside of the second dielectric layer.

Abstract: According to one embodiment, an arithmetic device, includes a first processing layer and a second processing layer, each configured to perform an arithmetic operation on input data and constituting a part of a multi-layer neural network configured to perform corrections by an error backward propagation scheme; a detour path that connects an input and an output of the second processing layer; and an evaluation unit configured to evaluate operation results of the first and the second processing layers.