Abstract: Embodiments provide an etchant composition that includes about 5.0 to about 20.0 wt % of a persulfate, about 0.01 to about 15.0 wt % of a sulfonic acid, about 0.01 to about 2.0 wt % of a fluorine compound, about 0.01 to about 5.0 wt % of a 4-nitrogen cyclic compound, about 0.01 to about 1.0 wt % of an amino acid including a hydrophobic group having at least two carbon atoms, and water A weight ratio of the amino acid to the 4-nitrogen cyclic compound is in a range of about 1:16 to about 1:60.

Abstract: Disclosed is a bit line-manufacturing method, by which a bit line having a fine width can be easily manufactured. The method comprises the steps of: successively forming a conducting layer and an insulating layer on a substrate, the conducting layer serving to form a bit line; forming a first mask pattern on the insulating layer in such a manner that a desired region of the insulating layer is exposed; etching the first mask pattern, so as to form a second mask pattern; removing the insulating layer using the second mask pattern; removing the second mask pattern; and removing the conducting layer using the remaining insulating layer as a mask, so as to form the bit line.

Abstract: Disclosed is a bit line-manufacturing method, by which a bit line having a fine width can be easily manufactured. The method comprises the steps of: successively forming a conducting layer and an insulating layer on a substrate, the conducting layer serving to form a bit line; forming a first mask pattern on the insulating layer in such a manner that a desired region of the insulating layer is exposed; etching the first mask pattern, so as to form a second mask pattern; removing the insulating layer using the second mask pattern; removing the second mask pattern; and removing the conducting layer using the remaining insulating layer as a mask, so as to form the bit line.

Abstract: A method for manufacturing a contact hole in a semiconductor device which includes the steps of preparing an active matrix provided with a substrate and word lines formed on the substrate, forming an etching barrier layer on the word lines and the substrate, forming an interlayer insulating layer on the etching barrier layer, forming a photoresist pattern on the interlayer insulating layer for defining a contact hole, etching the interlayer insulating layer under conditions of low polymerization until the etching barrier layer on the word lines is exposed, etching the interlayer insulating layer under conditions of high polymerization, and etching the interlayer insulating layer under conditions of low polymerization until the etching barrier layer in a bottom of the contact hole is exposed.

Abstract: A method for forming fine patterns and a using the method for forming gate electrodes of a semiconductor device are provided. The gate electrodes are formed by: forming a gate insulation layer over a semiconductor wafer; forming a conductive layer for the gate electrodes over the gate insulation layer; forming a low-dielectric layer over the conductive layer for the gate electrodes; forming a photoresist pattern whose width is equal to the exposure limit on the low-dielectric layer; patterning the low-dielectric layer using the photoresist pattern as a mask; removing the photoresist pattem; shrinking the low-dielectric pattern; and patterning the conductive layer for gate electrodes and the gate insulation layer using the shrunken low-dielectric pattern as a mask, thereby forming the gate electrodes.

Abstract: A method for manufacturing a contact hole in a semiconductor device which includes the steps of preparing an active matrix provided with a substrate and word lines formed on the substrate, forming an etching barrier layer on the word lines and the substrate, forming an interlayer insulating layer on the etching barrier layer, forming a photoresist pattern on the interlayer insulating layer for defining a contact hole, etching the interlayer insulating layer under conditions of low polymerization until the etching barrier layer on the word lines is exposed, etching the interlayer insulating layer under conditions of high polymerization, and etching the interlayer insulating layer under conditions of low polymerization until the etching barrier layer in a bottom of the contact hole is exposed.

Abstract: A method for manufacturing a gate electrode, the method including the steps of forming upon a semiconductor substrate a polysilicon layer, a metal nitride layer, a tungsten layer and a photoresist layer, patterning the photoresist layer on the tungsten layer into a predetermined configuration, etching the tungsten layer, the metal nitride layer, a portion of the polysilicon layer into the predetermined configuration by using a mixed etchant of fluorine and chlorine species etchant, and patterning the remaining polysilicon layer into the predetermined configuration by using chlorine etchant.

Abstract: A vibration damping alloy has a mixed structure of martensite and austenite. The alloy steel is iron-based to which 14-22% by weight of manganese is added. The vibration damping alloy is manufactured by mixing electrolytic iron and manganese in a molten state. The molten mixture, containing 14-22% of manganese with the remainder of iron, is cast as an ingot. The ingot is homogenized at 1000.degree.-1300.degree. C. for 20-40 hours and then hot rolled at 900.degree.-1100.degree. C. for 20 minutes to 90 minutes. The ingot is cooled with air or water.