Abstract: Methods of forming a semiconductor device are provided. The methods may include forming a second insulation pattern on a first insulation pattern. The first insulation pattern may cover a plurality of conductive structures, and may include a hole therein. The second insulation pattern may include a trench therein that is connected with the hole. The methods may also include forming a spacer on sidewalls of the hole and the trench. The methods may further include forming a wiring structure in the hole and the trench.

Abstract: Methods of forming a semiconductor device are provided. The methods may include forming a second insulation pattern on a first insulation pattern. The first insulation pattern may cover a plurality of conductive structures, and may include a hole therein. The second insulation pattern may include a trench therein that is connected with the hole. The methods may also include forming a spacer on sidewalls of the hole and the trench. The methods may further include forming a wiring structure in the hole and the trench.

Abstract: Provided is a method of forming a semiconductor device. A tunnel insulating layer is formed on a substrate having a cell region and a low voltage region. First and second charge storage gate patterns (e.g., floating gate patterns) are formed on the tunnel insulating layers of the cell and low voltage region, respectively. A blocking insulating layer and a control gate conductive layer are formed on the substrate in sequence. The control gate conductive layer, the blocking insulating layer, the second floating gate pattern and the tunnel insulating layer of the low voltage region are removed to expose the substrate of the low voltage region. The low-voltage gate insulating layer is formed on the exposed substrate. A low-voltage gate conductive pattern is formed on the low-voltage gate insulating layer.

Abstract: Semiconductor integrated circuit devices having SRAM cells and flash memory cells are provided. The devices include an integrated circuit substrate having an SRAM cell region, a flash memory cell region and a logic circuit region. An isolation layer is provided in a predetermined region of the substrate. The isolation layer defines a SRAM cell active region, a flash memory cell active region and a logic transistor active region in the SRAM cell region, the flash memory cell region and the logic circuit region, respectively. An SRAM cell gate pattern crosses over the SRAM cell active region. The SRAM cell gate pattern includes a main gate electrode and a dummy gate electrode which are sequentially stacked. A flash memory cell gate pattern crosses over the flash memory cell active region.

Abstract: Provided is a method of forming a semiconductor device. A tunnel insulating layer is formed on a substrate having a cell region and a low voltage region. First and second charge storage gate patterns (e.g., floating gate patterns) are formed on the tunnel insulating layers of the cell and low voltage region, respectively. A blocking insulating layer and a control gate conductive layer are formed on the substrate in sequence. The control gate conductive layer, the blocking insulating layer, the second floating gate pattern and the tunnel insulating layer of the low voltage region are removed to expose the substrate of the low voltage region. The low-voltage gate insulating layer is formed on the exposed substrate. A low-voltage gate conductive pattern is formed on the low-voltage gate insulating layer.

Abstract: Semiconductor integrated circuit devices having SRAM cells and flash memory cells are provided. The devices include an integrated circuit substrate having an SRAM cell region, a flash memory cell region and a logic circuit region. An isolation layer is provided in a predetermined region of the substrate. The isolation layer defines a SRAM cell active region, a flash memory cell active region and a logic transistor active region in the SRAM cell region, the flash memory cell region and the logic circuit region, respectively. An SRAM cell gate pattern crosses over the SRAM cell active region. The SRAM cell gate pattern includes a main gate electrode and a dummy gate electrode which are sequentially stacked. A flash memory cell gate pattern crosses over the flash memory cell active region.

Abstract: A borderless contact structure and method of forming thereof are provided. A device isolation region having a protrusion is formed at a predetermined region of a semiconductor substrate. The top surface of the protrusion is higher in level than that of the semiconductor substrate. An impurity diffusion region is formed in an active region surrounded by the device isolation region. An etch stop spacer is formed on a sidewall of the protrusion. An etch stop layer and an interlayer insulating layer are sequentially formed on the resultant structure including the impurity diffusion region, the device isolation region and the etch stop spacer. A contact hole opening the interlayer insulating layer and the etch stop layer is formed to expose at least a portion of the impurity diffusion region.

Abstract: A full CMOS SRAM cell includes first and second active regions formed in a semiconductor substrate. A word line traverses first and second areas of the second active region, and first and second gate electrodes are arranged to be perpendicular to the word line. The first and second gate electrodes are parallel to each other and traverse the first and second active regions, respectively. A power line is electrically connected to a first common source region and is arranged parallel to the word line, the first common source region being the first active region between the first gate electrode and the second gate electrode. A ground line is electrically connected to a second common source region and is arranged parallel to the word line, the second common source region being the second active region between the first gate electrode and the second gate electrode. First and second bit lines are arranged to be perpendicular to the word line and parallel to each other.

Abstract: A full CMOS SRAM cell includes first and second active regions formed in a semiconductor substrate. A word line traverses first and second areas of the second active region, and first and second gate electrodes are arranged to be perpendicular to the word line. The first and second gate electrodes are parallel to each other and traverse the first and second active regions, respectively. A power line is electrically connected to a first common source region and is arranged parallel to the word line, the first common source region being the first active region between the first gate electrode and the second gate electrode. A ground line is electrically connected to a second common source region and is arranged parallel to the word line, the second common source region being the second active region between the first gate electrode and the second gate electrode. First and second bit lines are arranged to be perpendicular to the word line and parallel to each other.

Abstract: A full CMOS SRAM cell includes first and second active regions formed in a semiconductor substrate. A word line traverses first and second areas of the second active region, and first and second gate electrodes are arranged to be perpendicular to the word line. The first and second gate electrodes are parallel to each other and traverse the first and second active regions, respectively. A power line is electrically connected to a first common source region and is arranged parallel to the word line, the first common source region being the first active region between the first gate electrode and the second gate electrode. A ground line is electrically connected to a second common source region and is arranged parallel to the word line, the second common source region being the second active region between the first gate electrode and the second gate electrode. First and second bit lines are arranged to be perpendicular to the word line and parallel to each other.

Abstract: A full CMOS SRAM cell is provided. The SRAM cell includes first and second active regions formed on a semiconductor substrate, arranged parallel to each other. A third active region is formed on the semiconductor substrate between the first active region and the second active region parallel to the first active region, and a fourth active region is formed on the semiconductor substrate between the third active region and the second active region parallel to the second active region. A word line intersects the first and second active regions. A first common conductive electrode intersects the first active region and the third active region, and a second common conductive electrode intersects the second active region and the fourth active region.

Abstract: A full CMOS SRAM cell is provided. The SRAM cell includes first and second active regions formed on a semiconductor substrate, arranged parallel to each other. A third active region is formed on the semiconductor substrate between the first active region and the second active region parallel to the first active region, and a fourth active region is formed on the semiconductor substrate between the third active region and the second active region parallel to the second active region. A word line intersects the first and second active regions. A first common conductive electrode intersects the first active region and the third active region, and a second common conductive electrode intersects the second active region and the fourth active region.

Abstract: A borderless contact structure and method of forming thereof are provided. A device isolation region having a protrusion is formed at a predetermined region of a semiconductor substrate. The top surface of the protrusion is higher in level than that of the semiconductor substrate. An impurity diffusion region is formed in an active region surrounded by the device isolation region. An etch stop spacer is formed on a sidewall of the protrusion. An etch stop layer and an interlayer insulating layer are sequentially formed on the resultant structure including the impurity diffusion region, the device isolation region and the etch stop spacer. A contact hole opening the interlayer insulating layer and the etch stop layer is formed to expose at least a portion of the impurity diffusion region.

Abstract: Integrated circuit SRAM cells include a semiconductor substrate having a field region and first, second, third and fourth active regions therein. The first and second active regions each include a horizontal leg and a vertical leg and are mirror images of each other about a vertical axis. The third and fourth active regions each also include a horizontal leg and a vertical leg and are mirror images of each other about a vertical axis. The integrated circuit SRAM cells also include first and second vertically extending gate conductive layers on the semiconductor substrate. The first vertically extending conductive layer extends vertically over the first active region horizontal leg and extends vertically over the third active region horizontal leg. The second vertically extending conductive layer extends vertically over the second active region horizontal leg and extends vertically over the fourth active region horizontal leg.

Abstract: The present invention relates to a semiconductor device which has not only high performance memory and logic by forming the low voltage and high voltage BiCMOS transistors in the same single semiconductor substrate,but also various functions and driving voltages by increasing the output power and noise margin, wherein the miniaturization of electronic products can be achieved by forming the low and high voltage BiCMOS transistors with various functions and also can achieve the high speed operation since a signal processing speed becomes fast.

Abstract: Integrated circuit SRAM cells include a semiconductor substrate having a field region and first, second, third and fourth active regions therein. The first and second active regions each include a horizontal leg and a vertical leg and are mirror images of each other about a vertical axis. The third and fourth active regions each also include a horizontal leg and a vertical leg and are mirror images of each other about a vertical axis. The integrated circuit SRAM cells also include first and second vertically extending gate conductive layers on the semiconductor substrate. The first vertically extending conductive layer extends vertically over the first active region horizontal leg and extends vertically over the third active region horizontal leg. The second vertically extending conductive layer extends vertically over the second active region horizontal leg and extends vertically over the fourth active region horizontal leg.