Abstract: A semiconductor device drive circuit includes: a first transistor and a second transistor operating complementarily between a first voltage and a second voltage lower than the first voltage; an internal power supply circuit operating between the first voltage and the second voltage, and including: a constant voltage generation unit outputting an internal power supply voltage steadily being a constant voltage; and a feedback unit receiving a node voltage of a connection node between the first transistor and the second transistor, and changing the internal power supply voltage output from the constant voltage generation unit in response to a change of the node voltage; and a pre-driver operating between the first voltage and the internal power supply voltage, and driving the first transistor or the second transistor, wherein the node voltage is output as a gate voltage of the power switching device.

Abstract: A semiconductor device includes a first switch and a first driver. The first switch selects and outputs one of a power supply potential and a generated potential as a first switch output potential based on a synchronization signal from a transmission circuit and a delayed signal delayed from the synchronization signal. The first driver charges a gate of a bipolar transistor element based on the synchronization signal of the transmission circuit and the first switch output potential.

Abstract: An object of the present disclosure is to provide a semiconductor device drive circuit stably preventing an erroneous operation in accordance with an application of dV/dt. A semiconductor device drive circuit includes: pulse transmission circuits outputting an on-pulse transmission signal and an off-pulse transmission signal based on a level shift on-pulse signal and a level shift off-pulse signal; a dV/dt detection circuit detecting a dV/dt period based on the level shift on-pulse signal and the level shift off-pulse signal; a logic filter circuit which does not change outputs when both the on-pulse transmission signal and the off-pulse transmission signal are input; and a latch circuit outputting a signal synchronized with an output of the logic filter circuit. The pulse transmission circuit includes impedance adjusting parts reducing a signal level of the on-pulse transmission signal and the off-pulse transmission signal during the dV/dt period.

Abstract: An object of the present disclosure is to provide a semiconductor device drive circuit stably preventing an erroneous operation in accordance with an application of dV/dt. A semiconductor device drive circuit includes: pulse transmission circuits outputting an on-pulse transmission signal and an off-pulse transmission signal based on a level shift on-pulse signal and a level shift off-pulse signal; a dV/dt detection circuit detecting a dV/dt period based on the level shift on-pulse signal and the level shift off-pulse signal; a logic filter circuit which does not change outputs when both the on-pulse transmission signal and the off-pulse transmission signal are input; and a latch circuit outputting a signal synchronized with an output of the logic filter circuit. The pulse transmission circuit includes impedance adjusting parts reducing a signal level of the on-pulse transmission signal and the off-pulse transmission signal during the dV/dt period.

Abstract: An object of the present invention is to reduce a chip area of the high-side driver circuit. A high-side driver circuit of the present invention is a high-side driver circuit in which a first potential is set as a power supply potential, which includes a constant voltage circuit configured to operate with a second potential as a reference potential, and generate, from the first potential, a third potential which is lower than the first potential and higher than the second potential, a logic circuit configured to operate with the third potential as a reference potential, a level shift circuit configured to shift the reference potential of the output signal of the logic circuit from the third potential to the second potential, and a driver circuit in which the second potential is set as a reference potential, and configured to drive a switching element by the output signal.

Abstract: An object of the present invention is to reduce a chip area of the high-side driver circuit. A high-side driver circuit of the present invention is a high-side driver circuit in which a first potential is set as a power supply potential, which includes a constant voltage circuit configured to operate with a second potential as a reference potential, and generate, from the first potential, a third potential which is lower than the first potential and higher than the second potential, a logic circuit configured to operate with the third potential as a reference potential, a level shift circuit configured to shift the reference potential of the output signal of the logic circuit from the third potential to the second potential, and a driver circuit in which the second potential is set as a reference potential, and configured to drive a switching element by the output signal.