Abstract: A filp-flop circuit includes master latch including a first inverter and a first tri-state inverter, wherein the first tri-state inverter includes a first NMOS transistor and a first PMOS transistor; a slave latch including a second inverter and a second tri-state inverter, wherein the second tri-state inverter includes a second PMOS transistor and a second NMOS transistor; and at least one of a first wiring configured to connect a source of the first PMOS transistor and a source of the first NMOS transistor and a second wiring configured to connect a source of the second PMOS transistor and a source of the second NMOS transistor.

Abstract: A measuring system (500), a communication component (200; 300a; 300b; 300c; 600; 700), a device (20), a process (10) and computer program of a communication component (200; 300a; 300b; 300c; 600; 700) of a measuring system (500) are provided. The measuring system (500) includes an additional communication component (200; 300a; 300b; 300c; 600; 700). The process (10) for the communication component (200; 300a; 300b, 300c; 600; 700) of the measuring system (500) includes management (11) of at least one personalized user with access rights in the measuring system (500) and storage (12) of access data for the at least one personalized user. Synchronization (13) of the access data of the at least one personalized user with the one or more additional communication components (200; 300a; 300b; 300c; 600; 700) is provided.

Abstract: A D-type flip-flop circuit 1 has a structure in which a pMOS transistor p8 and an nMOS transistor n8 are added to a general D-type flip-flop circuit comprising pMOS transistors p1 to p7, p11 to p15 and nMOS transistors n1 to n7, n11 to n15.

Abstract: A D-type flip-flop circuit 1 has a structure in which a pMOS transistor p8 and an nMOS transistor n8 are added to a general D-type flip-flop circuit comprising pMOS transistors p1 to p7, p11 to p15 and nMOS transistors n1 to n7, n11 to n15.

Abstract: A flip-flop circuit (FF 10) of the present invention includes master latch circuits (LAT 11 and LAT 12), slave latch circuits (LAT 13 and LAT 14), C-element circuits (CE 11, CE 12, CE 13, and CE 14), and inverter circuits (INV 11, INV 12, INV 13, and INV 14). The inverter circuits (INV 11 and INV 12) are interconnected to each other between the C-element circuit (CE 11) and the C-element circuit (CE 12). The inverter circuits (INV 13 and INV 14) are interconnected to each other between the C-element circuit (CE 13) and the C-element circuit (CE 14).

Abstract: A flip-flop circuit (FF 10) of the present invention includes master latch circuits (LAT 11 and LAT 12), slave latch circuits (LAT 13 and LAT 14), C-element circuits (CE 11, CE 12, CE 13, and CE 14), and inverter circuits (INV 11, INV 12, INV 13, and INV 14). The inverter circuits (INV 11 and INV 12) are interconnected to each other between the C-element circuit (CE 11) and the C-element circuit (CE 12). The inverter circuits (INV 13 and INV 14) are interconnected to each other between the C-element circuit (CE 13) and the C-element circuit (CE 14).

Abstract: An electronic money system has an IC card for electronic money having a memory for maintaining money deposit and money debit information and another memory, such as an EPROM, for storing transaction data, including detailed information of transactions, such as the content of a typical receipt received from a retail store. The transaction information can be used at a later time in a personal computer so that an electronic record of household expenses can be maintained The transaction data that is stored includes the product name, price of the product, quantity of the product purchased and similar details of the transaction. The IC card memory can record the name and telephone number of a retail store where the card has been used or a network address can be recorded in the memory for use by a customer to access electronic direct-mail information by using a PC.