Patents by Inventor Jun-gang LI

Jun-gang LI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145442
    Abstract: An embodiment of an LED lamp that generates light of a color temperature that decreases with decreasing power applied to the LED lamp may include at least one lighting arrangement that may include a first LED array of serially connected first LED chips, a second LED array of serially connected second LED chips; a first photoluminescence layer covering the first LED array for generating light of a first color temperature; a second photoluminescence layer covering the second LED array for generating light of a second different color temperature; and a linear resistor serially connected to the first LED array, wherein the first LED array and second LED array are connected in parallel.
    Type: Application
    Filed: January 7, 2024
    Publication date: May 2, 2024
    Inventors: Yi-Qun Li, Jun-Gang Zhao, Gang Wang
  • Patent number: 10562718
    Abstract: A variable spacing device includes a support member, a driving member, a number of movable graspers, a limiting block, and a pushing block. The movable graspers are slidably mounted in a line on the support member. Each movable grasper grasps a workpiece. The limiting block is mounted on the support member and arranged in parallel with the pushing member. The limiting block defines first sliding grooves having a length gradually decreasing along a same direction. The pushing block defines second sliding grooves having a length gradually increasing along a same direction. Each movable grasper moves within a corresponding one of the first sliding grooves and a corresponding one of the second sliding grooves. Two sidewalls of each first sliding groove and two sidewalls of each second sliding groove resist movement of the corresponding movable grasper.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: February 18, 2020
    Assignees: Fu Tai Hua Industry (Shenzhen) Co., Ltd., HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Wei-Da Yang, Li-Quan Zhang, Qing Cai, Jun-Gang Li
  • Patent number: 8775885
    Abstract: The present invention relates to an IEEE1588 protocol negative testing method, comprises steps of: connecting a IEEE1588 tester and a slave clock DUT to establish a real-time closed-loop feedback mechanism; taking the IEEE1588 tester as a master clock, and establishing a stable time synchronization with the slave clock DUT; obtaining the timing offset or path delay of the slave clock DUT before disturbance; assembling an abnormal message in a frame and sending it to the slave clock DUT; calculating the timing offset or path delay increment after disturbance of the abnormal message; determining whether there is a sudden change in the timing offset or path delay of the slave clock DUT, wherein if there is no sudden change, the test passes; otherwise the test fails.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: July 8, 2014
    Assignees: Xu Ji Group Corporation, State Grid Corporation of China
    Inventors: Xiao-hui Song, Yong Wei, Fu-sheng Li, Quan-sheng Cui, Jun-feng Di, Jun-gang Li, Yun-zhao Zheng, Hong-guang Shi, Tuo-fu Zheng, Yi-ding Song, Bao-shan Zhang
  • Publication number: 20130103997
    Abstract: The present invention relates to an IEEE1588 protocol negative testing method, comprises steps of: connecting a IEEE1588 tester and a slave clock DUT to establish a real-time closed-loop feedback mechanism; taking the IEEE1588 tester as a master clock, and establishing a stable time synchronization with the slave clock DUT; obtaining the timing offset or path delay of the slave clock DUT before disturbance; assembling an abnormal message in a frame and sending it to the slave clock DUT; calculating the timing offset or path delay increment after disturbance of the abnormal message; determining whether there is a sudden change in the timing offset or path delay of the slave clock DUT, wherein if there is no sudden change, the test passes; otherwise the test fails.
    Type: Application
    Filed: August 28, 2012
    Publication date: April 25, 2013
    Applicants: STATE GRID CORPORATION OF CHINA, XU JI GROUP CORPORATION
    Inventors: Xiao-hui SONG, Yong WEI, Fu-sheng LI, Quan-sheng CUI, Jun-feng DI, Jun-gang LI, Yun-zhao ZHENG, Hong-guang SHI, Tuo-fu ZHENG, Yi-ding SONG, Bao-shan ZHANG