Patents by Inventor Jun-Goo Kang
Jun-Goo Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250079135Abstract: A deposition apparatus including: a base substrate; an electrostatic chuck on the base substrate; and a plate on the electrostatic chuck. The plate has a first area in which first magnet units are arranged and a second area in which second magnet units are arranged. The first magnet units are spaced apart from each other at a first distance, and the second magnet units are spaced apart from each other at a second distance. The second distance is greater than the first distance.Type: ApplicationFiled: June 10, 2024Publication date: March 6, 2025Inventors: Jun Hyeuk KO, Jong Bum KIM, Young Kwang LEE, Min Goo KANG, Suk Ha RYU, Min Chul SONG, Min A WOO
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Publication number: 20240234485Abstract: An integrated circuit device includes a conductive region on a substrate and a lower electrode structure including a main electrode part spaced apart from the conductive region and a bridge electrode part between the main electrode part and the conductive region. A dielectric layer contacts an outer sidewall of the main electrode part. To manufacture the integrated circuit device, a preliminary bridge electrode layer is formed in a hole of a mold pattern on the substrate, and the main electrode part is formed on the preliminary bridge electrode layer in the hole. The mold pattern is removed to expose a sidewall of the preliminary bridge electrode layer, and a portion of the preliminary electrode part is removed to form the bridge electrode part. The dielectric layer is formed to contact the outer sidewall of the main electrode part.Type: ApplicationFiled: March 25, 2024Publication date: July 11, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: Jun-goo KANG, Hyun-suk LEE, Gi-hee CHO
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Patent number: 12009387Abstract: An integrated circuit device includes a conductive region on a substrate and a lower electrode structure including a main electrode part spaced apart from the conductive region and a bridge electrode part between the main electrode part and the conductive region. A dielectric layer contacts an outer sidewall of the main electrode part. To manufacture the integrated circuit device, a preliminary bridge electrode layer is formed in a hole of a mold pattern on the substrate, and the main electrode part is formed on the preliminary bridge electrode layer in the hole. The mold pattern is removed to expose a sidewall of the preliminary bridge electrode layer, and a portion of the preliminary electrode part is removed to form the bridge electrode part. The dielectric layer is formed to contact the outer sidewall of the main electrode part.Type: GrantFiled: May 18, 2021Date of Patent: June 11, 2024Assignee: Samsung Electronics, Co. Ltd.Inventors: Jun-goo Kang, Hyun-suk Lee, Gi-hee Cho
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Patent number: 11978765Abstract: An integrated circuit device includes a conductive region on a substrate and a lower electrode structure including a main electrode part spaced apart from the conductive region and a bridge electrode part between the main electrode part and the conductive region. A dielectric layer contacts an outer sidewall of the main electrode part. To manufacture the integrated circuit device, a preliminary bridge electrode layer is formed in a hole of a mold pattern on the substrate, and the main electrode part is formed on the preliminary bridge electrode layer in the hole. The mold pattern is removed to expose a sidewall of the preliminary bridge electrode layer, and a portion of the preliminary electrode part is removed to form the bridge electrode part. The dielectric layer is formed to contact the outer sidewall of the main electrode part.Type: GrantFiled: May 18, 2021Date of Patent: May 7, 2024Assignee: Samsung Electronics, Co. Ltd.Inventors: Jun-goo Kang, Hyun-suk Lee, Gi-hee Cho
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Patent number: 11812601Abstract: A semiconductor device includes a substrate, first and second supporter patterns stacked sequentially on the substrate in a first direction and spaced apart from an upper surface of the substrate, a lower electrode hole that extends through the first and second supporter patterns on the substrate in the first direction, an interface film on side walls and a bottom surface of the lower electrode hole, a lower electrode inside of the lower electrode hole on the interface film, a capacitor dielectric film that is in physical contact with side walls of the interface film, an uppermost surface of the interface film, and an uppermost surface of the lower electrode, the uppermost surface of the interface film is formed on a same plane as an upper surface of the second supporter pattern.Type: GrantFiled: April 1, 2021Date of Patent: November 7, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Jun Goo Kang, Sang Hyuck Ahn, Sang Yeol Kang, Jin-Su Lee, Hyun-Suk Lee, Gi Hee Cho, Hong Sik Chae
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Publication number: 20230158211Abstract: The present invention relates to a hyaluronic acid-based hydrogel which is a hyaluronic acid-peptide crosslinked body crosslinked using a peptide crosslinking agent. More specifically, the present invention relates to a hyaluronic acid-based hydrogel and a method for producing same, wherein a crosslinked body having novel physical properties is obtained using a relatively small amount of a crosslinking agent that forms peptide bonds, unlike conventional crosslinking agents, and the hyaluronic acid-based hydrogel has the advantages of: being safe and having few side effects; the physical properties of a filler being adjustable according to the amount of peptide crosslinking; and having a high elasticity ratio.Type: ApplicationFiled: March 16, 2021Publication date: May 25, 2023Inventors: Kyeong-Yong PARK, Jun-Goo KANG, Seoung Jin LEE, Sok Jin KIM
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Patent number: 11588012Abstract: A method of manufacturing a semiconductor device includes forming a preliminary lower electrode layer on a substrate, the preliminary lower electrode layer including a niobium oxide; converting at least a portion of the preliminary lower electrode layer to a first lower electrode layer comprising a niobium nitride by performing a nitridation process on the preliminary lower electrode layer; forming a dielectric layer on the first lower electrode layer; and forming an upper electrode on the dielectric layer.Type: GrantFiled: March 12, 2021Date of Patent: February 21, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-goo Kang, Sang-yeol Kang, Youn-soo Kim, Jin-su Lee, Hyung-suk Jung, Kyu-ho Cho
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Publication number: 20220037325Abstract: A semiconductor device includes a substrate, first and second supporter patterns stacked sequentially on the substrate in a first direction and spaced apart from an upper surface of the substrate, a lower electrode hole that extends through the first and second supporter patterns on the substrate in the first direction, an interface film on side walls and a bottom surface of the lower electrode hole, a lower electrode inside of the lower electrode hole on the interface film, a capacitor dielectric film that is in physical contact with side walls of the interface film, an uppermost surface of the interface film, and an uppermost surface of the lower electrode, the uppermost surface of the interface film is formed on a same plane as an upper surface of the second supporter pattern.Type: ApplicationFiled: April 1, 2021Publication date: February 3, 2022Inventors: Jun Goo Kang, Sang Hyuck Ahn, Sang Yeol Kang, Jin-Su Lee, Hyun-Suk Lee, Gi Hee Cho, Hong Sik Chae
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Publication number: 20210273041Abstract: An integrated circuit device includes a conductive region on a substrate and a lower electrode structure including a main electrode part spaced apart from the conductive region and a bridge electrode part between the main electrode part and the conductive region. A dielectric layer contacts an outer sidewall of the main electrode part. To manufacture the integrated circuit device, a preliminary bridge electrode layer is formed in a hole of a mold pattern on the substrate, and the main electrode part is formed on the preliminary bridge electrode layer in the hole. The mold pattern is removed to expose a sidewall of the preliminary bridge electrode layer, and a portion of the preliminary electrode part is removed to form the bridge electrode part. The dielectric layer is formed to contact the outer sidewall of the main electrode part.Type: ApplicationFiled: May 18, 2021Publication date: September 2, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Jun-goo KANG, Hyun-suk LEE, Gi-hee CHO
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Publication number: 20210202693Abstract: A method of manufacturing a semiconductor device includes forming a preliminary lower electrode layer on a substrate, the preliminary lower electrode layer including a niobium oxide; converting at least a portion of the preliminary lower electrode layer to a first lower electrode layer comprising a niobium nitride by performing a nitridation process on the preliminary lower electrode layer; forming a dielectric layer on the first lower electrode layer; and forming an upper electrode on the dielectric layer.Type: ApplicationFiled: March 12, 2021Publication date: July 1, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Jun-goo KANG, Sang-yeol KANG, Youn-soo KIM, Jin-su LEE, Hyung-suk JUNG, Kyu-ho CHO
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Patent number: 11031460Abstract: An integrated circuit device includes a conductive region on a substrate and a lower electrode structure including a main electrode part spaced apart from the conductive region and a bridge electrode part between the main electrode part and the conductive region. A dielectric layer contacts an outer sidewall of the main electrode part. To manufacture the integrated circuit device, a preliminary bridge electrode layer is formed in a hole of a mold pattern on the substrate, and the main electrode part is formed on the preliminary bridge electrode layer in the hole. The mold pattern is removed to expose a sidewall of the preliminary bridge electrode layer, and a portion of the preliminary electrode part is removed to form the bridge electrode part. The dielectric layer is formed to contact the outer sidewall of the main electrode part.Type: GrantFiled: August 29, 2019Date of Patent: June 8, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-goo Kang, Hyun-suk Lee, Gi-hee Cho
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Patent number: 10978552Abstract: A method of manufacturing a semiconductor device includes forming a preliminary lower electrode layer on a substrate, the preliminary lower electrode layer including a niobium oxide; converting at least a portion of the preliminary lower electrode layer to a first lower electrode layer comprising a niobium nitride by performing a nitridation process on the preliminary lower electrode layer; forming a dielectric layer on the first lower electrode layer; and forming an upper electrode on the dielectric layer.Type: GrantFiled: February 12, 2019Date of Patent: April 13, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jun-goo Kang, Sang-yeol Kang, Youn-soo Kim, Jin-su Lee, Hyung-suk Jung, Kyu-ho Cho
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Publication number: 20200266265Abstract: An integrated circuit device includes a conductive region on a substrate and a lower electrode structure including a main electrode part spaced apart from the conductive region and a bridge electrode part between the main electrode part and the conductive region. A dielectric layer contacts an outer sidewall of the main electrode part. To manufacture the integrated circuit device, a preliminary bridge electrode layer is formed in a hole of a mold pattern on the substrate, and the main electrode part is formed on the preliminary bridge electrode layer in the hole. The mold pattern is removed to expose a sidewall of the preliminary bridge electrode layer, and a portion of the preliminary electrode part is removed to form the bridge electrode part. The dielectric layer is formed to contact the outer sidewall of the main electrode part.Type: ApplicationFiled: August 29, 2019Publication date: August 20, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Jun-goo Kang, Hyun-suk Lee, Gi-hee Cho
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Publication number: 20190355806Abstract: A method of manufacturing a semiconductor device includes forming a preliminary lower electrode layer on a substrate, the preliminary lower electrode layer including a niobium oxide; converting at least a portion of the preliminary lower electrode layer to a first lower electrode layer comprising a niobium nitride by performing a nitridation process on the preliminary lower electrode layer; forming a dielectric layer on the first lower electrode layer; and forming an upper electrode on the dielectric layer.Type: ApplicationFiled: February 12, 2019Publication date: November 21, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Jun-goo KANG, Sang-yeol Kang, Youn-soo Kim, Jin-su Lee, Hyung-suk Jung, Kyu-ho CHO
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Patent number: 9773861Abstract: A capacitor may include a lower electrode structure, a dielectric layer on the lower electrode structure, and an upper electrode on the dielectric layer. The lower electrode structure may include first to third lower electrodes sequentially stacked, a first oxidation barrier pattern structure between the first lower electrode and the second lower electrode, and a second oxidation barrier pattern structure between the second lower electrode and the third lower electrode. The first oxidation barrier pattern structure may include first and second oxidation barrier patterns sequentially stacked on the first lower electrode, and the second oxidation barrier pattern structure may include third and fourth oxidation barrier patterns sequentially stacked on the second lower electrode.Type: GrantFiled: March 8, 2016Date of Patent: September 26, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-Suk Lee, Jun-Goo Kang
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Publication number: 20160380044Abstract: A capacitor may include a lower electrode structure, a dielectric layer on the lower electrode structure, and an upper electrode on the dielectric layer. The lower electrode structure may include first to third lower electrodes sequentially stacked, a first oxidation barrier pattern structure between the first lower electrode and the second lower electrode, and a second oxidation barrier pattern structure between the second lower electrode and the third lower electrode. The first oxidation barrier pattern structure may include first and second oxidation barrier patterns sequentially stacked on the first lower electrode, and the second oxidation barrier pattern structure may include third and fourth oxidation barrier patterns sequentially stacked on the second lower electrode.Type: ApplicationFiled: March 8, 2016Publication date: December 29, 2016Inventors: Hyun-Suk LEE, Jun-Goo KANG
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Patent number: 9525926Abstract: An acoustic camera for using a MEMS microphone array comprises: an acoustic sensor apparatus (30) comprising a print circuit board (20) on which the plural of MEMS microphone (10) are mounted, to send signals for the detected sound to a data collection unit (40); a data collection unit (40) connected to the acoustic sensor apparatus (30), which samples analog signals related to sound transmitted from the acoustic sensor apparatus (30) to transform into digital signals and transmit them to the central processing unit (40); a central processing unit (50) connected to the data collection unit (40), which calculates noise level based on digital signals related to sound transmitted from the data collection unit (40); and a display unit (60) which is connected to the central processing unit (50), which displays in color the noise level calculated at the central processing unit.Type: GrantFiled: August 19, 2011Date of Patent: December 20, 2016Assignee: SM INSTRUMENT CO., LTD.Inventors: Young-Gi Kim, Kang-Hyun Lee, Jun-Goo Kang