Patents by Inventor Jun Gu

Jun Gu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260147400
    Abstract: In various examples, systems and methods are disclosed relating to part-invariant peak power management. One or more circuits can receive a plurality of instructions for a graphics processing device. The plurality of instructions can correspond to a respective plurality of power consumption values. The one or more circuits can determine that the respective plurality of power consumption values cause a threshold to be exceeded during a time period. The one or more circuits can generate a control signal to control a clock signal for the graphics processing device responsive to determining that the respective plurality of power consumption values cause the threshold to be exceeded.
    Type: Application
    Filed: November 27, 2024
    Publication date: May 28, 2026
    Applicant: NVIDIA Corporation
    Inventors: Vandana Bansal, Brian Smith, Jun Gu, Vishal Mehta
  • Patent number: 12619565
    Abstract: Embodiments of the present disclosure provide a system and method to simulate property values generated by Desktop Bus (D-Bus) objects. According to one embodiment, an Information Handling System (IHS) includes multiple D-Bus services that communicate among one another using a D-Bus with executable instructions to generate a D-Bus simulation service that communicates with one or more other D-Bus services through a D-Bus, and sends simulation test data to one of the other D-Bus services in response to a request from the one other D-Bus service.
    Type: Grant
    Filed: October 19, 2023
    Date of Patent: May 5, 2026
    Assignee: Dell Products L.P.
    Inventors: Jun Gu, Arun Muthaiyan, Thomas William Erdman, Kang Quan
  • Patent number: 12592778
    Abstract: An apparatus comprises at least one processing device configured to receive, at a first hardware component of an information technology asset, sideband management data for the information technology asset. The at least one processing device is also configured to utilize a first light-based communication module of the first hardware component to convert the received sideband management data into one or more visible light communication signals. The at least one processing device is further configured to transmit the received sideband management data by providing the one or more visible light communication signals from the first light-based communication module of the first hardware component of the information technology asset to a second light-based communication module of a second hardware component of the information technology asset.
    Type: Grant
    Filed: September 29, 2023
    Date of Patent: March 31, 2026
    Assignee: Dell Products L.P.
    Inventors: Shree Rathinasamy, Yayun Liu, Jun Gu
  • Publication number: 20260035342
    Abstract: There are provided isotope-enriched compounds of Formula (I) and pharmaceutically acceptable salts or esters thereof, as well as pharmaceutical compositions thereof and methods of use thereof for prevention and treatment and amyloid-? related diseases, such as Alzheimer's disease.
    Type: Application
    Filed: October 7, 2025
    Publication date: February 5, 2026
    Inventors: Jiasheng LU, Jiamin GU, Xinyong LV, Guowei SONG, Dongdong WU, Daiqiang HU, Jun GU, Gang CHEN, Xiang JI, Xiuchun ZHANG, Jinchao AI, Xianqi KONG
  • Patent number: 12459888
    Abstract: There are provided isotope-enriched compounds of Formula (I) and pharmaceutically acceptable salts or esters thereof, as well as pharmaceutical compositions thereof and methods of use thereof for prevention and treatment of amyloid-? related diseases, such as Alzheimer's disease.
    Type: Grant
    Filed: January 19, 2024
    Date of Patent: November 4, 2025
    Assignee: RISEN (SUZHOU) PHARMA TECH CO., LTD.
    Inventors: Jiasheng Lu, Jiamin Gu, Xinyong Lv, Guowei Song, Dongdong Wu, Daiqiang Hu, Jun Gu, Gang Chen, Xiang Ji, Xiuchun Zhang, Jinchao Ai, Xianqi Kong
  • Patent number: 12424846
    Abstract: An integrated circuit that includes multiple power rails with dummy loads configured on at least some of the power rails. The dummy loads are activated in response to a voltage overshoot condition on regions of the power rails at which the dummy loads are located. The dummy loads may be substituted for decoupling capacitors or other active cells at particular regions of the power rails.
    Type: Grant
    Filed: March 20, 2023
    Date of Patent: September 23, 2025
    Assignee: NVIDIA Corp.
    Inventors: Tezaswi Raja, Abhishek B Akkur, Jun Gu, Chengcheng Liu
  • Patent number: 12401635
    Abstract: Methods, apparatus, and processor-readable storage media for automatically generating task-based and limited-privilege user security credentials are provided herein. An example computer-implemented method includes processing a request for user security credentials against one or more predetermined security parameters associated with at least one network; generating, based on the processing of the request, at least one set of user security credentials comprising one or more combinations of multiple randomly selected characters; configuring one or more attributes associated with the at least one set of user security credentials in connection with the at least one network, wherein the one or more attributes comprise at least one of one or more task-related attributes and one or more privilege-related attributes; and performing one or more automated actions based on the one or more configured attributes and/or implementation of the at least one set of user security credentials by one or more users.
    Type: Grant
    Filed: October 18, 2022
    Date of Patent: August 26, 2025
    Assignee: Dell Products L.P.
    Inventors: Farhan Syed, Deepaganesh Paulraj, Douglas J. Roberts, Colby Harper, Jason C. Dale, Jun Gu
  • Patent number: 12391019
    Abstract: A dispensing system includes a container, a roll of slit paper, and a passive tension mechanism. The container includes panels and one of the panels includes a dispensing aperture. The slit paper on the roll is in an unexpanded state. The slit paper can be transformed from the unexpanded state to an expanded state by exerting a longitudinal pulling force on the slit paper. The passive tension mechanism is in the container and arranged such that a path of the slit paper from the roll to the dispensing aperture passes through the passive tension mechanism. The passive tension mechanism is configured to induce tension in the slit paper along the path between the roll of the slit paper and the dispensing aperture such that the slit paper transforms from the unexpanded state to the expanded state along the path between the roll of the slit paper and the dispensing aperture.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: August 19, 2025
    Assignee: FAGERDALA SINGAPORE PTE LTD
    Inventors: Mun Fei Cho, Jun Gu, Szu Hui Lim, Chee Keong Yap, George Guicas
  • Patent number: 12385015
    Abstract: Provided is a method for constructing a gE protein-deleted pseudorabies virus (PRV) strain using an adenine base editor (ABE) and use thereof. The method includes: designing an sgRNA sequence using the ABE with a start codon of the gE gene in a PRV as a target site, ligating an enzyme-digested fragment to a double-stranded DNA fragment with sticky ends to obtain a ligation product; and transforming the ligation product into a competent cell to allow plate screening and culture, selecting a resulting positive bacterial strain to allow expanded culture, and extracting a plasmid from a resulting positive bacterial solution; and transferring the plasmid into a target cell to allow the transfection for 24 h, collecting a resulting virus liquid, and centrifuging the virus liquid to collect a resulting supernatant.
    Type: Grant
    Filed: October 1, 2024
    Date of Patent: August 12, 2025
    Assignee: JIANGXI AGRICULTURAL UNIVERSITY
    Inventors: Yu Ye, Peixia Wang, Yuxin Tang, Chuan Zeng, Jun Gu, Jinyan Shen, Yiwen Duan, Yuwei Bai, Dongyan Huang, Deping Song
  • Publication number: 20250225290
    Abstract: According to embodiments of the disclosure, there are provided a method, an apparatus, a device, and a storage medium for evaluating a power supply design. The method includes determining a power supply network designed for a chip, the power supply network comprising a plurality of power supply lines for power transmission and indicating a position and a pattern of each of the plurality of power supply lines in the chip. The method includes generating, for the power supply network, an electrical configuration at least associated with a predetermined power consumption of the chip. The method includes determining predicted voltage losses at different positions of the power supply network with the electrical configuration. In this way, fast evaluation and verification of the power supply solution can be implemented, which is beneficial to shorten the cycle of the chip design.
    Type: Application
    Filed: March 27, 2025
    Publication date: July 10, 2025
    Inventors: Liangliang Jin, Jun Gu, Jifeng Li, Jian Wang
  • Publication number: 20250171243
    Abstract: The disclosure relates to a new cassette logistics system comprising a conveyor to transfer a cassette and a cleaning and measuring station. The conveyor is configured to moves the cassette in a first direction. The cleaning and measuring station is positioned at a location along the conveyor such that the cassette is received at the cleaning and measurement station when the cassette has moved a predetermined distance in the first direction. The cleaning and measuring station has both a cleaning port and a measurement port. The cleaning port is configured to removed debris on surfaces of the cassette and the measurement port is configured to measure contents of the cassette after the debris has been removed.
    Type: Application
    Filed: March 7, 2023
    Publication date: May 29, 2025
    Inventors: Xu Cao, Jun Gu, Jun Yuan Hou
  • Publication number: 20250136951
    Abstract: Provided is a method for constructing a gE gene-deleted pseudorabies virus (PRV) strain using an adenine base editor (ABE) and use thereof. The method includes: designing an sgRNA sequence using the ABE with a start codon of the gE gene in a PRV as a target site, ligating an enzyme-digested fragment to a double-stranded DNA fragment with sticky ends to obtain a ligation product; and transforming the ligation product into a competent cell to allow plate screening and culture, selecting a resulting positive bacterial strain to allow expanded culture, and extracting a plasmid from a resulting positive bacterial solution; and transferring the plasmid into a target cell to allow the transfection for 24 h, collecting a resulting virus liquid, and centrifuging the virus liquid to collect a resulting supernatant.
    Type: Application
    Filed: October 1, 2024
    Publication date: May 1, 2025
    Applicant: JIANGXI AGRICULTURAL UNIVERSITY
    Inventors: Yu YE, Peixia WANG, Yuxin TANG, Chuan ZENG, Jun GU, Jinyan SHEN, Yiwen DUAN, Yuwei BAI, Dongyan HUANG, Deping SONG
  • Publication number: 20250130829
    Abstract: Embodiments of the present disclosure provide a system and method to simulate hardware devices on an Information Handling System (IHS). According to one embodiment, an Information Handling System (IHS) includes executable instructions to receive, from an application, one or more first messages intended to be sent to a yet-to-be-developed hardware device using at least one software interface associated with the communication links, and generate one or more second messages that simulate a behavior of the missing hardware device. The second message may then be sent to the application to simulate the yet-to-be-developed hardware device.
    Type: Application
    Filed: October 19, 2023
    Publication date: April 24, 2025
    Applicant: Dell Products, L.P.
    Inventors: Jun Gu, Arun Muthaiyan, Kang Quan, Sayali Prafulla Kesari
  • Publication number: 20250130965
    Abstract: Embodiments of the present disclosure provide a system and method to simulate property values generated by Desktop Bus (D-Bus) objects. According to one embodiment, an Information Handling System (IHS) includes multiple D-Bus services that communicate among one another using a D-Bus with executable instructions to generate a D-Bus simulation service that communicates with one or more other D-Bus services through a D-Bus, and sends simulation test data to one of the other D-Bus services in response to a request from the one other D-Bus service.
    Type: Application
    Filed: October 19, 2023
    Publication date: April 24, 2025
    Applicant: Dell Products, L.P.
    Inventors: Jun Gu, Arun Muthaiyan, Thomas William Erdman, Kang Quan
  • Publication number: 20250112704
    Abstract: An apparatus comprises at least one processing device configured to receive, at a first hardware component of an information technology asset, sideband management data for the information technology asset. The at least one processing device is also configured to utilize a first light-based communication module of the first hardware component to convert the received sideband management data into one or more visible light communication signals. The at least one processing device is further configured to transmit the received sideband management data by providing the one or more visible light communication signals from the first light-based communication module of the first hardware component of the information technology asset to a second light-based communication module of a second hardware component of the information technology asset.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Inventors: Shree Rathinasamy, Yayun Liu, Jun Gu
  • Publication number: 20240371747
    Abstract: A circuit assembly includes an IC die and a stack of capacitor dies. The IC die has a first hybrid bonding layer. The stack of capacitor dies includes a first capacitor die and a second capacitor die. The first capacitor die has a second hybrid bonding layer in contact with the first hybrid bonding layer. The second capacitor die is stacked over the first capacitor die. The first capacitor die has a third hybrid bonding layer. The second capacitor die has a fourth hybrid bonding layer coupled to the third hybrid bonding layer. The second capacitor die has a first side and a second side, the fourth hybrid bonding layer is formed on the second side, a plurality of conductive vias is formed on the first side, and the second capacitor die further comprises a plurality of interface bumps electrically connecting to the conductive vias.
    Type: Application
    Filed: July 17, 2024
    Publication date: November 7, 2024
    Applicant: AP Memory Technology Corp.
    Inventors: Wenliang CHEN, Jun GU, Masaru HARAGUCHI, Takashi KUBO, Chien-An YU, Chun Yi LIN
  • Patent number: 12105652
    Abstract: An information handling system may include a management controller and a chassis having mounted therein at least one add-in card. The management controller may be configured to: retrieve connection information from the add-in card, the connection information indicating a physical location of the add-in card within the chassis; compare the connection information with expected connection information associated with the information handling system; determine that the physical location of the add-in card within the chassis is in conflict with a restriction associated with the add-in card; and transmit an error message based on the determining.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: October 1, 2024
    Assignee: Dell Products L.P.
    Inventors: Robert R. Leyendecker, Jun Gu, Chien-Lin Lee, Jon Vernon Franklin
  • Publication number: 20240322559
    Abstract: An integrated circuit that includes multiple power rails with dummy loads configured on at least some of the power rails. The dummy loads are activated in response to a voltage overshoot condition on regions of the power rails at which the dummy loads are located. The dummy loads may be substituted for decoupling capacitors or other active cells at particular regions of the power rails.
    Type: Application
    Filed: March 20, 2023
    Publication date: September 26, 2024
    Applicant: NVIDIA Corp.
    Inventors: Tezaswi Raja, Abhishek B Akkur, Jun Gu, Chengcheng Liu
  • Patent number: 12074103
    Abstract: A circuit assembly includes an integrated circuit (IC) die and a capacitor die. The IC die has a first hybrid bonding layer. The capacitor die is stacked with the IC die, and is configured to include a capacitor coupled to the IC die, and has a second hybrid bonding layer in contact with the first hybrid bonding layer; wherein the IC die is electrically coupled to the capacitor die through the first hybrid bonding layer and the second hybrid bonding layer.
    Type: Grant
    Filed: June 1, 2022
    Date of Patent: August 27, 2024
    Assignee: AP Memory Technology Corp.
    Inventors: Wenliang Chen, Jun Gu, Masaru Haraguchi, Takashi Kubo, Chien-An Yu, Chun Yi Lin
  • Patent number: 12042897
    Abstract: The present disclosure provides a grinding wheel cutting apparatus comprising a first laser distance sensor, a master controller and a grinding wheel. The first laser distance sensor is communicatively coupled to the master controller. The laser distance sensor is configured to obtain an outer diameter of a rod workpiece. The master controller is configured to determine a segment length of a segment to be cut from the rod workpiece based on the outer diameter, a material density of the rod workpiece and a preset segment weight. The master controller is configured to perform a control to circularly cut the rod workpiece with the grinding wheel according to the segment length. The present disclosure further relates to a cutting method using the grinding wheel cutting apparatus.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: July 23, 2024
    Assignees: BIAM ALLOYS CO., LTD., JIUMA AUTOMATIC MACHINERY (SHANGHAI) CO., LTD.
    Inventors: Gang Liu, Xiafei Zhou, Yu Meng, Hongbo Li, Jun Gu, Xujie Wan