Abstract: A water purifier is provided. A water purifier according to one aspect of the present invention may include a housing having a first accommodation space therein, and made of a paper material; a water purifier faucet disposed in the first accommodation space to receive raw water and discharge purified water; and a filter coupled to the water purifier faucet to generate the purified water by filtering the raw water, wherein the water purifier faucet includes a base frame having a second accommodation space therein in which the filter is accommodated; a water inlet module provided on one side of the base frame to supply raw water introduced from the outside to the filter; and a water outlet module provided on the other side of the base frame to receive the purified water generated by the filter and discharge it to the outside.

Abstract: An integrated circuit chip includes an SOI substrate having a structure in which a bulk substrate, a buried insulating film, and a semiconductor body layer are sequentially stacked, a conductive ion implantation region formed at a position adjacent to the buried insulating film in the bulk substrate, an integrated circuit portion formed on an active surface of the semiconductor body layer, and a penetrating electrode portion arranged at a position spaced apart from the integrated circuit portion in a horizontal direction, the penetrating electrode portion penetrating the semiconductor body layer and the buried insulating layer in a vertical direction, and the penetrating electrode portion connected to the conductive ion implantation region. An integrated circuit package and a display device include the integrated circuit chip.

Abstract: A semiconductor device includes; an active region extending in a first horizontal direction on a substrate, source/drain regions disposed on the active region, a buried trench formed between the source/drain regions, a buried insulating layer surrounding both side walls of the buried trench in the first horizontal direction between the source/drain regions, a wing trench formed in a lower part of the buried trench and having a width greater than a width of the buried trench, and a gate electrode extending in a second horizontal direction on the active region, and disposed within each of the buried trench and the wing trench.

Abstract: A semiconductor device includes: a substrate including first and second regions thereon; a first active region in the first region; an active pattern protruding from the first active region; a second active region in the second region; a first gate electrode on the active pattern; a second gate electrode on the second active region; a first gate insulating layer, including a first-first insulating layer, between the active pattern and the first gate electrode; and a second gate insulating layer, including a second-first insulating layer and a second-second insulating layer below the second-first insulating layer, between the second active region and the second gate electrode, wherein a thickness in a vertical direction of the first gate electrode that overlaps the active pattern in the vertical direction is equal to a thickness in the vertical direction of the second gate electrode that overlaps the second active region in the vertical direction, and an upper surface of the first gate electrode is formed at a

Abstract: The present invention provides an apparatus for protecting dental patient hearing through noise reduction, the apparatus comprising: a main body portion provided in a form that can be mounted on both ears of a user; a microphone module that is provided on one side of the main body portion and collects external sound signals generated from the outside; a noise filter module that is built in the main body portion and filters the external sound signals to block or reduces noise signals included in the external sound signals; and a speaker module that is built in the main body portion and provided on the other side of the main body portion corresponding to the ears of the user, and that outputs sound signals filtered by the noise filter module.

Abstract: An integrated circuit (IC) chip includes a via contact plug extending inside a through hole passing through a substrate and a device layer, a via contact liner surrounding the via contact plug, a connection pad liner extending along a bottom surface of the substrate, a dummy bump structure integrally connected to the via contact plug, and a bump structure connected to the connection pad liner. A method of manufacturing an IC chip includes forming an under bump metallurgy (UBM) layer inside and outside the through hole and forming a first connection metal layer, a second connection metal layer, and a third connection metal layer. The first connection metal layer covers the UBM layer inside the through hole, the second connection metal layer is integrally connected to the first connection metal layer, and the third connection metal layer covers the UBM layer on the connection pad liner.

Abstract: A system for establishing a dental treatment environment, includes: a head-mounted device provided at a dental clinic to be mounted on a patient's head, the head-mounted device having an image display unit and an ear-mounted speaker, a microphone for converting a sound including the voice of the medical staff in charge of the patient into an electric signal; a voice recognition module for recognizing the voice of the medical staff in charge from the electric sound input from the microphone; a content module storing multiple image contents for relaxing the patient mentally physically; a user interface having a content selection unit configured such that the patient can select a play content provided to the image display unit from the multiple image contents; and an output signal generating module for generating an output signal that is output to the head-mounted device.

Abstract: A sound control system for dental treatment, includes: ear-worn speakers equipped to be worn by a patient in the dentist; a microphone that converts, into an electrical signal, a sound including the voice of a medical staff in charge of the patient; a voice recognition module for recognizing the voice of the medical staff in charge from an electrical sound signal input from the microphone; a sound source module that stores a plurality of sound sources for mental and physical stability of the patient; a user interface including a sound source selection unit that allows the patient to select a play sound source provided via the ear-worn speakers from among the plurality of sound sources; and an output signal generation module for generating an output sound signal output via the ear-worn speakers.

Abstract: An integrated circuit chip includes an SOI substrate having a structure in which a bulk substrate, a buried insulating film, and a semiconductor body layer are sequentially stacked, a conductive ion implantation region formed at a position adjacent to the buried insulating film in the bulk substrate, an integrated circuit portion formed on an active surface of the semiconductor body layer, and a penetrating electrode portion arranged at a position spaced apart from the integrated circuit portion in a horizontal direction, the penetrating electrode portion penetrating the semiconductor body layer and the buried insulating layer in a vertical direction, and the penetrating electrode portion connected to the conductive ion implantation region. An integrated circuit package and a display device include the integrated circuit chip.

Abstract: An integrated circuit chip includes an SOI substrate having a structure in which a bulk substrate, a buried insulating film, and a semiconductor body layer are sequentially stacked, a conductive ion implantation region formed at a position adjacent to the buried insulating film in the bulk substrate, an integrated circuit portion formed on an active surface of the semiconductor body layer, and a penetrating electrode portion arranged at a position spaced apart from the integrated circuit portion in a horizontal direction, the penetrating electrode portion penetrating the semiconductor body layer and the buried insulating layer in a vertical direction, and the penetrating electrode portion connected to the conductive ion implantation region. An integrated circuit package and a display device include the integrated circuit chip.

Abstract: A semiconductor device includes: a substrate including a first region and a second region; a first gate stack on the first region of the substrate; a first source/drain contact at a first side of the first gate stack, wherein the first source/drain contact is connected to the substrate; a second gate stack on the second region of the substrate; and a second source/drain contact at a first side of the second gate stack, wherein the second source/drain contact is connected to the substrate, wherein a height of the second source/drain contact is greater than a height of the first source/drain contact, and wherein a width of the second source/drain contact is greater than a width of the first source/drain contact.

Abstract: An integrated circuit (IC) chip includes a via contact plug extending inside a through hole passing through a substrate and a device layer, a via contact liner surrounding the via contact plug, a connection pad liner extending along a bottom surface of the substrate, a dummy bump structure integrally connected to the via contact plug, and a bump structure connected to the connection pad liner. A method of manufacturing an IC chip includes forming an under bump metallurgy (UBM) layer inside and outside the through hole and forming a first connection metal layer, a second connection metal layer, and a third connection metal layer. The first connection metal layer covers the UBM layer inside the through hole, the second connection metal layer is integrally connected to the first connection metal layer, and the third connection metal layer covers the UBM layer on the connection pad liner.

Abstract: An integrated circuit chip includes a circuit structure, a grounding structure, a bonding layer between the circuit structure and the grounding structure. The circuit structure includes a first substrate, an FEOL structure, and a BEOL structure. The grounding structure includes a second substrate and a grounding conductive layer. The integrated circuit chip includes a first penetrating electrode portion connected to the grounding conductive layer based on extending through the first substrate, the FEOL structure, the BEOL structure, and the bonding layer such that the first penetrating electrode portion is isolated from direct contact with the integrated circuit portion in a horizontal direction extending parallel to an active surface of the first substrate. An integrated circuit package and a display device each include the integrated circuit chip.

Abstract: A semiconductor device includes: a substrate including a first region and a second region; a first gate stack on the first region of the substrate; a first source/drain contact at a first side of the first gate stack, wherein the first source/drain contact is connected to the substrate; a second gate stack on the second region of the substrate; and a second source/drain contact at a first side of the second gate stack, wherein the second source/drain contact is connected to the substrate, wherein a height of the second source/drain contact is greater than a height of the first source/drain contact, and wherein a width of the second source/drain contact is greater than a width of the first source/drain contact.

Abstract: An integrated circuit (IC) chip includes a via contact plug extending inside a through hole passing through a substrate and a device layer, a via contact liner surrounding the via contact plug, a connection pad liner extending along a bottom surface of the substrate, a dummy bump structure integrally connected to the via contact plug, and a bump structure connected to the connection pad liner. A method of manufacturing an IC chip includes forming an under bump metallurgy (UBM) layer inside and outside the through hole and forming a first connection metal layer, a second connection metal layer, and a third connection metal layer. The first connection metal layer covers the UBM layer inside the through hole, the second connection metal layer is integrally connected to the first connection metal layer, and the third connection metal layer covers the UBM layer on the connection pad liner.

Abstract: A semiconductor device includes a substrate, in which a lower semiconductor layer, an insulating gapfill layer, and an upper semiconductor layer are sequentially stacked. A gate structure is disposed on the upper semiconductor layer. A source/drain electrode is disposed on a sidewall of the gate structure. A semiconductor pattern is disposed between the source/drain electrode and the upper semiconductor layer. The gate structure includes a gate electrode and a spacer structure. The spacer structure includes a first spacer pattern, a second spacer pattern, and a third spacer pattern, sequentially disposed on a sidewall of the gate electrode. The semiconductor pattern is extended to a region below a bottom surface of the third spacer pattern and is connected to the second spacer pattern.

Abstract: A semiconductor device includes a substrate, in which a lower semiconductor layer, an insulating gapfill layer, and an upper semiconductor layer are sequentially stacked. A gate structure is disposed on the upper semiconductor layer. A source/drain electrode is disposed on a sidewall of the gate structure. A semiconductor pattern is disposed between the source/drain electrode and the upper semiconductor layer. The gate structure includes a gate electrode and a spacer structure. The spacer structure includes a first spacer pattern, a second spacer pattern, and a third spacer pattern, sequentially disposed on a sidewall of the gate electrode. The semiconductor pattern is extended to a region below a bottom surface of the third spacer pattern and is connected to the second spacer pattern.

Abstract: A semiconductor device is provided. The semiconductor device comprises a substrate, a gate electrode on the substrate, an element isolation film in the substrate and spaced apart from the gate electrode, an impurity region between the element isolation film and the gate electrode, the impurity region including a first impurity of a first concentration, and a depletion buffer region on at least a part of side walls of the element isolation film, the depletion buffer region including a second impurity of a second concentration higher than the first concentration, a conductivity type of the second impurity being the same as a conductivity type of the first impurity.

Abstract: A semiconductor device includes: a substrate including a first region and a second region; a first gate stack on the first region of the substrate; a first source/drain contact at a first side of the first gate stack, wherein the first source/drain contact is connected to the substrate; a second gate stack on the second region of the substrate; and a second source/drain contact at a first side of the second gate stack, wherein the second source/drain contact is connected to the substrate, wherein a height of the second source/drain contact is greater than a height of the first source/drain contact, and wherein a width of the second source/drain contact is greater than a width of the first source/drain contact.

Abstract: An integrated circuit (IC) chip includes a via contact plug extending inside a through hole passing through a substrate and a device layer, a via contact liner surrounding the via contact plug, a connection pad liner extending along a bottom surface of the substrate, a dummy bump structure integrally connected to the via contact plug, and a bump structure connected to the connection pad liner. A method of manufacturing an IC chip includes forming an under bump metallurgy (UBM) layer inside and outside the through hole and forming a first connection metal layer, a second connection metal layer, and a third connection metal layer. The first connection metal layer covers the UBM layer inside the through hole, the second connection metal layer is integrally connected to the first connection metal layer, and the third connection metal layer covers the UBM layer on the connection pad liner.