Abstract: A novel compound for a capping layer, and an organic light-emitting device containing the same are disclosed.

Abstract: A novel compound for a capping layer, and an organic light-emitting device containing the same are disclosed.

Abstract: The present invention provides an immunogenic composition comprising a Streptococcus pneumoniae polysaccharide-protein conjugate, comprising a capsular polysaccharide derived from one or more selected from the group consisting of serotypes 1, 2, 3, 4, 5, 6A, 6B, 7F, 8, 9N, 9V, 10A, 11A, 12F, 14, 15B, 17F, 18C, 19A, 19F, 20, 22F, 23F, and 33F, derived from Streptococcus pneumoniae; and one or 2 or more of carrier proteins conjugated to the respective capsular polysaccharide, and method of preparation thereof. Through one example of the present invention, an immunogenic composition for preventing or treating pneumococcal infection can be provided.

Abstract: A device includes a display and a housing. The housing surrounds the display and has four corners defining portions of an exterior surface of the device. The housing includes a first housing segment defining at least part of a first corner of the four corners and configured to operate as an antenna; a second housing segment defining at least part of a second corner of the four corners; and a third housing segment defining at least part of a third corner of the four corners. The third corner forms part of the housing diagonally opposite the second corner. The housing further includes a non-conductive housing component that structurally couples the first housing segment to another portion of the housing.

Abstract: A wireless communication system, according to one embodiment of the present invention, comprises: a first communication module; and at least one second communication module wirelessly connected to the first communication module, wherein the first communication module is wirelessly connected to the second communication module to which driving power is applied from the same power source as that of the first communication module.

Abstract: A DNN accelerator system includes a plurality of accelerator nodes each including a plurality of NAND flash memories, a flash memory system (FMS) controller for controlling the plurality of NAND flash memories, and a tensor buffer, and a processor configured to generate an operation sequence of the plurality of accelerator nodes, in which a DNN model is trained in a data parallel manner using the plurality of accelerator nodes.

Abstract: A processor-implemented method with scheduling includes: receiving one or more execution requests for a plurality of models executed independently of each other in an accelerator; predicting, for each of the plurality of models, quality of service (QoS) information corresponding to the model; and scheduling the plurality of models in units of layers of the plurality of models based on, for each of the plurality of models, either one or both of the QoS information and an idle time occurring in response to a candidate layer to be scheduled in the model being executed in the accelerator.

Abstract: An accelerator includes a key matrix register configured to store a key matrix, a query vector register configured to store a query vector; and a preprocessor configured to calculate similarities between the query vector and the key matrix.

Abstract: A hardware accelerator includes a block processing circuit configured to read a block from a list stored in an inverted index structure; and a search core configured to extract a document number out of a read block read by the block processing circuit and to calculate a score corresponding to the document number.

Abstract: Disclosed is a method for processing a page fault. The method includes performing demand paging depending on an application operation in a system including a processor and an operating system, and loading, at the processor, data on a memory in response to the demand paging.

Abstract: A processor, a method of operating the processor, and an electronic device including the processor are disclosed. The method includes arranging, in respective input registers, weights and activations having a smaller number of bits than a minimum operation unit of an operator included in the processor, performing a multiplication between values stored in the input registers, storing a result of the multiplication in an output register, and outputting, from the output register, a value in a preset bit range as a result of a dot product between a first vector including the weights and a second vector including the activations.

Abstract: A device includes a display and a housing. The housing at least partially surrounds the display. The housing includes a first housing segment defining at least a first portion of an exterior surface of the device and a first interlock feature having an interlock surface that is offset with respect to an end surface of the first housing segment. The first interlock feature has a first opening formed in the interlock surface. The housing further includes a second housing segment defining at least a second portion of the exterior surface of the device and a second interlock feature having a second opening aligned with the first opening, and a non-conductive housing component defining a third portion of the exterior surface of the device and extending into the first opening and the second opening.

Abstract: A device includes a display and a housing. The housing surrounds the display and has four corners defining portions of an exterior surface of the device. The housing includes a first housing segment defining at least part of a first corner of the four corners and configured to operate as an antenna; a second housing segment defining at least part of a second corner of the four corners; and a third housing segment defining at least part of a third corner of the four corners. The third corner forms part of the housing diagonally opposite the second corner. The housing further includes a non-conductive housing component that structurally couples the first housing segment to another portion of the housing.

Abstract: A device includes a display and a housing. The housing surrounds the display and has four corners defining portions of an exterior surface of the device. The housing includes a first housing segment defining at least part of a first corner of the four corners and configured to operate as an antenna; a second housing segment defining at least part of a second corner of the four corners; and a third housing segment defining at least part of a third corner of the four corners. The third corner forms part of the housing diagonally opposite the second corner. The housing further includes a non-conductive housing component that structurally couples the first housing segment to another portion of the housing.

Abstract: A scheduler, a method of operating the scheduler, and an accelerator apparatus including the scheduler are disclosed. A method of operating a scheduler to perform scheduling on models to be executed in an accelerator, the method includes receiving at least one execution request for a first model and a second model that are executed independently from each other in the accelerator, and performing layer-unit scheduling on the first model and the second model based on workload characteristics of the first model and the second model.

Abstract: Disclosed is a method for processing a page fault. The method includes performing demand paging depending on an application operation in a system including a processor and an operating system, and loading, at the processor, data on a memory in response to the demand paging.

Abstract: A hardware accelerator includes a block processing circuit configured to read a block from a list stored in an inverted index structure; and a search core configured to extract a document number out of a read block read by the block processing circuit and to calculate a score corresponding to the document number.

Abstract: A device includes a display and a housing. The housing at least partially surrounds the display. The housing includes a first housing segment defining at least a first portion of an exterior surface of the device and a first interlock feature having an interlock surface that is offset with respect to an end surface of the first housing segment. The first interlock feature has a first opening formed in the interlock surface. The housing further includes a second housing segment defining at least a second portion of the exterior surface of the device and a second interlock feature having a second opening aligned with the first opening, and a non-conductive housing component defining a third portion of the exterior surface of the device and extending into the first opening and the second opening.

Abstract: The disclosure is directed to a multi-segment housing for an electronic device that includes multiple conductive segments that are structurally coupled by one or more non-conductive housing segments or splits. One or more of the conductive segments may be configured to operate as an antenna and the non-conductive housing segments may provide electrical insulation between the conductive segment and one or more adjacent housing segments. The non-conductive housing segment may be formed from a polymer having an array of fibers dispersed within the polymer. The fibers may be aligned along one or more fiber directions, which may be substantially perpendicular to an exterior surface of the housing.

Abstract: An accelerator includes a key matrix register configured to store a key matrix, a query vector register configured to store a query vector; and a preprocessor configured to calculate similarities between the query vector and the key matrix.