Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.

Abstract: A semiconductor device includes a substrate having a volatile memory region and a non-volatile memory region. The volatile memory region includes a cell capacitor disposed in the substrate and a cell transistor connected to the cell capacitor. The non-volatile memory region includes a plurality of non-volatile memory cells disposed on the substrate. The volatile memory region and the non-volatile memory region are disposed side by side.

Abstract: A semiconductor device includes a memory cell region including memory cells arranged along channel holes, the channel holes being provided on a substrate to extend in a direction perpendicular to an upper surface of the substrate, and a peripheral circuit region disposed outside of the memory cell region and including low voltage transistors and high voltage transistors. The low voltage transistors include first transistors including a first gate dielectric layer and a first gate electrode layer including a metal, and the high voltage transistors include second transistors including a second gate dielectric layer having a dielectric constant lower than a dielectric constant of the first gate dielectric layer, and a second gate electrode layer including polysilicon.

Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.

Abstract: A semiconductor device includes a memory cell region including memory cells arranged along channel holes, the channel holes being provided on a substrate to extend in a direction perpendicular to an upper surface of the substrate, and a peripheral circuit region disposed outside of the memory cell region and including low voltage transistors and high voltage transistors. The low voltage transistors include first transistors including a first gate dielectric layer and a first gate electrode layer including a metal, and the high voltage transistors include second transistors including a second gate dielectric layer having a dielectric constant lower than a dielectric constant of the first gate dielectric layer, and a second gate electrode layer including polysilicon.

Abstract: A vertical memory device and method of manufacture thereof are provided. The vertical memory device includes gate electrode layers stacked on a substrate; a channel layer penetrating through the gate electrode layers; and a first epitaxial layer in contact with a lower portion of the channel layer and including a region having a diameter smaller than an external diameter of the channel layer.

Abstract: A semiconductor device includes a memory cell region including memory cells arranged along channel holes, the channel holes being provided on a substrate to extend in a direction perpendicular to an upper surface of the substrate, and a peripheral circuit region disposed outside of the memory cell region and including low voltage transistors and high voltage transistors, The low voltage transistors include first transistors including a first gate dielectric layer and a first gate electrode layer including a metal, and the high voltage transistors include second transistors including a second gate dielectric layer having a dielectric constant lower than a dielectric constant of the first gate dielectric layer, and a second gate electrode layer including polysilicon.

Abstract: A vertical stack memory device includes a doped semiconductor substrate having a common source to which a source power is applied and a low band gap layer that is spaced apart from the common source, and the low band gap comprising low band gap materials. A stack gate structure has gate electrodes and insulation interlayer patterns that are alternately and vertically stacked on the substrate in a first direction. A channel structure penetrates through the stack gate structure in the first direction. The channel structure makes contact with the low hand gap layer. A charge storage structure is interposed between the stack gate structure and the channel structure. The charge storage structure is configured to selectively store charge and to provide the stored charge to a memory cell, the stack gate structure, and the channel structure.

Abstract: A semiconductor device includes first and second active regions extending in a first direction on a substrate and spaced apart from each other in a second direction intersecting the first direction, wherein the first and second active regions overlaps with each other in the second direction, a third active region extending in the first direction on the substrate and spaced apart from the first active region in the second direction. The first active region is positioned between the second and third active regions in the second direction. The first and third active regions partially overlap in the second direction, and a device isolation film is configured to define the first to third active regions.

Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.

Abstract: In a method of manufacturing a semiconductor device, a gate structure is formed on a substrate. An ion implantation process is performed at an upper portion of the substrate exposed by the gate structure, so that an ion implantation region is formed to have an expanded volume. The ion implantation process uses ions that are identical to a material of the substrate.

Abstract: A semiconductor device includes a semiconductor substrate having a first transistor region and a second transistor region, a first MOSFET including a first gate insulating layer structure and a first gate electrode structure, and a second MOSFET including a group IV compound semiconductor layer, a second gate insulating layer structure, and a second gate electrode structure. The first gate insulating layer structure and the first gate electrode structure are disposed on the first transistor region of the semiconductor substrate. The group IV compound semiconductor layer is disposed on the second transistor region of the semiconductor substrate, and the second gate insulating layer and the second gate electrode structure are disposed on the group IV compound semiconductor layer. Each of the first and second gate insulating layer structures includes a high-k dielectric (insulating) layer.

Abstract: A semiconductor device includes an active region defined on a substrate, a gate electrode disposed on the active region and covering two adjacent corners of the active region, a drain area formed in the active region adjacent to a first side of the gate electrode, and a source area formed in the active region adjacent to a second side of the gate electrode. The first and second sides of the gate electrode are spaced apart from each other, and the first side has a bent shape.

Abstract: A semiconductor device is provided. A cell region is disposed in a substrate. The cell region includes a memory cell. A peripheral region is disposed in the substrate. The peripheral region is adjacent to the cell region. The peripheral region has a trench isolation, a first active region and a second active region. The trench isolation is interposed between the first active region and the second active region. A common gate pattern is disposed on the peripheral region. The common gate pattern extends in a first direction and partially overlaps the first active region, the second active region and the trench isolation. A buried conductive pattern is enclosed by the trench isolation. The buried conductive pattern extends in a second direction crossing the first direction. A top surface of the buried conductive pattern is lower than a bottom surface of the common gate pattern.

Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including an active region on a substrate, the active region being defined by a field region; gate trenches in the active region of the substrate; gate structures respectively formed in the gate trenches; and at least one carrier barrier layer in the substrate and under the gate trenches.

Abstract: A method of forming a capacitor structure includes forming a mold layer on a substrate, in which the substrate includes a plurality of plugs therein, partially removing the mold layer to form a plurality of openings, in which the plugs are exposed by the openings, forming a plurality of lower electrodes filling the openings, in which the lower electrodes have a pillar shape, removing an upper portion of the mold layer to expose upper portions of the lower electrodes, forming a supporting pattern on exposed upper sidewalls of the lower electrodes and on the mold layer, removing the mold layer, and sequentially forming a dielectric layer and an upper electrode on the lower electrodes and the supporting pattern.

Abstract: In a method of manufacturing a semiconductor device, a gate structure is formed on a substrate. An ion implantation process is performed at an upper portion of the substrate exposed by the gate structure, so that an ion implantation region is formed to have an expanded volume. The ion implantation process uses ions that are identical to a material of the substrate.

Abstract: There is provided a semiconductor device. The semiconductor device may include multiple contacts plugs, an insulation layer pattern, a metal oxide layer pattern, a metal pattern and a metal line. The contact plugs contact a substrate. The insulation layer pattern is formed between the contact plugs and has a top surface lower than those of the contact plugs. The metal oxide layer pattern is formed on the insulation layer pattern, and has a dielectric constant higher than that of silicon oxide. The metal pattern is formed on the metal oxide layer pattern and contacts sidewalls of the contact plugs. The metal line contacts top surfaces of the contact plugs and the metal pattern and extends thereon.

Abstract: A semiconductor device is provided. The semiconductor device includes first and second storage electrodes formed to be spaced apart from each other on a substrate, an insulating continuous support pattern connected to top surfaces of the first and second storage electrodes, a storage dielectric layer formed to cover the first and second storage electrodes and the continuous support pattern, and a plate electrode formed on the storage dielectric layer. The continuous support pattern includes a first contact part connected to the top surface of the first storage electrode, a second contact part connected to the top surface of the second storage electrode, and a connection part connecting the first and second contact parts with each other.

Abstract: A semiconductor device includes an active region defined on a substrate, a gate electrode disposed on the active region and covering two adjacent corners of the active region, a drain area formed in the active region adjacent to a first side of the gate electrode, and a source area formed in the active region adjacent to a second side of the gate electrode. The first and second sides of the gate electrode are spaced apart from each other, and the first side has a bent shape.