Abstract: A vehicle seat includes first and second sub-seatbacks also provided as first and second seat cushions mounted on a main seatback to be rotatable in forward-rearward directions. A forward facing position in which an occupant is accommodated while viewing forward and a rearward facing position in which the occupant is accommodated while viewing rearward is easily realized, in response to forward and rearward rotation of the first sub-seatback and the second sub-seatback also provided as first and second seat cushions. Furthermore, a full-bed mode in which the seat is horizontally spread like a bed, a cushion tip-up mode in which the entirety of the seat is positioned upright for ensuring freight loading and an occupant entering and exiting passage, and the like are realized.

Abstract: The present invention relates to a primer set for detecting a trace amount of a rare single-nucleotide variant and a method for specifically and sensitively detecting a trace amount of a rare single-nucleotide variant by using same. Particularly, the present invention relates to: a primer composition for detecting a single-nucleotide variant (SNV), the primer composition comprising a first primer that comprises a nucleotide sequence complementary to a to-be-detected DNA fragment comprising an SNV to be detected, and at the 3? end of the primer, 2-6 nucleotide sequences that are not complementary to the to-be-detected DNA fragment; and a method for detecting a trace amount of a rare single-nucleotide variant, the method comprising performing a polymerase chain reaction (PCR) using the composition.

Abstract: A semiconductor memory device includes a stack structure on a substrate, extending in a first direction, and including gate electrode layers and insulating layers stacked alternately with each other, a vertical structure including a vertical channel film extending in a second direction crossing the first direction and a channel insulating film disposed on the vertical channel film and having first areas adjacent to the insulating layers and second areas adjacent to the gate electrode layers, and a high-k film on the channel insulating film. The high-k film includes a first high-k metal oxide film between the first areas and the insulating layers and in contact with the first areas and a second high-k metal oxide film between the second areas and the gate electrode layers and in contact with the second areas, and the first and second high-k metal oxide films include different metal materials.

Abstract: Provided is a segment-block-based handwritten signature authentication system and a method thereof, and more particularly, to a handwritten signature authentication system and a method thereof that enrolls a handwritten signature including handwritten signature characteristics information based on segment blocks disjointed by a user, acquires segment-block-based handwritten signature characteristics information from the handwritten signature upon request for handwritten signature authentication, and performs handwritten signature authentication by comparing the pre-enrolled handwritten signature characteristics information based on segments and the acquired handwritten signature characteristics information.

Abstract: Provided is a segment-block-based handwritten signature authentication system and a method thereof, and more particularly, to a handwritten signature authentication system and a method thereof that enrolls a handwritten signature including handwritten signature characteristics information based on segment blocks disjointed by a user, acquires segment-block-based handwritten signature characteristics information from the handwritten signature upon request for handwritten signature authentication, and performs handwritten signature authentication by comparing the pre-enrolled handwritten signature characteristics information based on segments and the acquired handwritten signature characteristics information.

Abstract: A memory module having an address mirroring function is provided. The memory module includes a register that allows mode registers of first memory chips of a first rank and mode registers of second memory chips of a second rank to be identically programmed in response to a mode register set (MRS) command during a rank-merged test mode. The register sets address signals, which are symmetrically connected to the first and second memory chips through through-via-holes (TVHs) or blind-via-holes (BVHs) of a printed circuit board, to be selectively mirrored.

Abstract: Provided is a system and method for authenticating a user according to login and financial transactions, such as payment and transfer, and more particularly, to a system and method for authentication using a quick response (QR) code, in which a quick response (QR) code including authentication information is displayed on the computer terminal of a user, the QR code is scanned through a smart device such as a smartphone, and the authentication is performed using the scanned QR code by accessing a QR authentication server included in the QR code.

Abstract: A memory module having an address minoring function is provided. The memory module includes a register that allows mode registers of first memory chips of a first rank and mode registers of second memory chips of a second rank to be identically programmed in response to a mode register set (MRS) command during a rank-merged test mode. The register sets address signals, which are symmetrically connected to the first and second memory chips through through-via-holes (TVHs) or blind-via-holes (BVHs) of a printed circuit board, to be selectively mirrored.

Abstract: A memory device includes a memory cell array and a data input/output circuit. The memory cell array includes a plurality of memory cells connected to a plurality of bit lines and a plurality of word lines. The data input/output circuit is configured to receive data from external data pins of the memory device, output the received data to the memory cell array through a plurality of input/output lines electrically coupled to the plurality of bit lines, receive data read from the memory cell array through the plurality of input/output lines, and output the read data through the external data pins. For each external data pin, the data input/output circuit is configured to output data received at the external data pin to a corresponding input/output line. The corresponding input/output line is selected in response to bit values of a set of bits included in the received data.

Abstract: A memory module comprises a plurality of semiconductor memory devices each comprising a mode register set (MRS) circuit configured to generate an enable signal corresponding to an error mode of the semiconductor memory device in response to an MRS command received from a command decoder, and an address buffer configured to store a predetermined address signal, to receive an address signal and corresponding data from an external device, and to compare the address signal received with the predetermined address signal in response to the enable signal. As a consequence of determining that the address signal received from the external device is the same as the predetermined address signal stored in the address buffer, data different from the corresponding data received from the external device is written to a memory cell corresponding to the predetermined address signal.

Abstract: A memory module comprises a plurality of semiconductor memory devices each comprising a mode register set (MRS) circuit configured to generate an enable signal corresponding to an error mode of the semiconductor memory device in response to an MRS command received from a command decoder, and an address buffer configured to store a predetermined address signal, to receive an address signal and corresponding data from an external device, and to compare the address signal received with the predetermined address signal in response to the enable signal. As a consequence of determining that the address signal received from the external device is the same as the predetermined address signal stored in the address buffer, data different from the corresponding data received from the external device is written to a memory cell corresponding to the predetermined address signal.

Abstract: A memory device includes a memory cell array and a data input/output circuit. The memory cell array includes a plurality of memory cells connected to a plurality of bit lines and a plurality of word lines. The data input/output circuit is configured to receive data from external data pins of the memory device, output the received data to the memory cell array through a plurality of input/output lines electrically coupled to the plurality of bit lines, receive data read from the memory cell array through the plurality of input/output lines, and output the read data through the external data pins. For each external data pin, the data input/output circuit is configured to output data received at the external data pin to a corresponding input/output line. The corresponding input/output line is selected in response to bit values of a set of bits included in the received data.