Patents by Inventor Jun Hee SHIN

Jun Hee SHIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10572715
    Abstract: Provided is a segment-block-based handwritten signature authentication system and a method thereof, and more particularly, to a handwritten signature authentication system and a method thereof that enrolls a handwritten signature including handwritten signature characteristics information based on segment blocks disjointed by a user, acquires segment-block-based handwritten signature characteristics information from the handwritten signature upon request for handwritten signature authentication, and performs handwritten signature authentication by comparing the pre-enrolled handwritten signature characteristics information based on segments and the acquired handwritten signature characteristics information.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: February 25, 2020
    Assignee: SECUVE CO., LTD.
    Inventors: Ki-Yoong Hong, Jun-Hee Shin
  • Publication number: 20190065822
    Abstract: Provided is a segment-block-based handwritten signature authentication system and a method thereof, and more particularly, to a handwritten signature authentication system and a method thereof that enrolls a handwritten signature including handwritten signature characteristics information based on segment blocks disjointed by a user, acquires segment-block-based handwritten signature characteristics information from the handwritten signature upon request for handwritten signature authentication, and performs handwritten signature authentication by comparing the pre-enrolled handwritten signature characteristics information based on segments and the acquired handwritten signature characteristics information.
    Type: Application
    Filed: October 5, 2016
    Publication date: February 28, 2019
    Inventors: Ki-Yoong HONG, Jun-Hee SHIN
  • Patent number: 9548091
    Abstract: A memory module having an address mirroring function is provided. The memory module includes a register that allows mode registers of first memory chips of a first rank and mode registers of second memory chips of a second rank to be identically programmed in response to a mode register set (MRS) command during a rank-merged test mode. The register sets address signals, which are symmetrically connected to the first and second memory chips through through-via-holes (TVHs) or blind-via-holes (BVHs) of a printed circuit board, to be selectively mirrored.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: January 17, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-Hee Shin, Sang-Jhun Hwang, Young-Man Ahn
  • Publication number: 20160314462
    Abstract: Provided is a system and method for authenticating a user according to login and financial transactions, such as payment and transfer, and more particularly, to a system and method for authentication using a quick response (QR) code, in which a quick response (QR) code including authentication information is displayed on the computer terminal of a user, the QR code is scanned through a smart device such as a smartphone, and the authentication is performed using the scanned QR code by accessing a QR authentication server included in the QR code.
    Type: Application
    Filed: November 13, 2014
    Publication date: October 27, 2016
    Inventors: Ki-Yoong HONG, Jun-Hee SHIN
  • Publication number: 20150340074
    Abstract: A memory module having an address minoring function is provided. The memory module includes a register that allows mode registers of first memory chips of a first rank and mode registers of second memory chips of a second rank to be identically programmed in response to a mode register set (MRS) command during a rank-merged test mode. The register sets address signals, which are symmetrically connected to the first and second memory chips through through-via-holes (TVHs) or blind-via-holes (BVHs) of a printed circuit board, to be selectively mirrored.
    Type: Application
    Filed: April 8, 2015
    Publication date: November 26, 2015
    Inventors: JUN-HEE SHIN, SANG-JHUN HWANG, YOUNG-MAN AHN
  • Patent number: 9164139
    Abstract: A memory device includes a memory cell array and a data input/output circuit. The memory cell array includes a plurality of memory cells connected to a plurality of bit lines and a plurality of word lines. The data input/output circuit is configured to receive data from external data pins of the memory device, output the received data to the memory cell array through a plurality of input/output lines electrically coupled to the plurality of bit lines, receive data read from the memory cell array through the plurality of input/output lines, and output the read data through the external data pins. For each external data pin, the data input/output circuit is configured to output data received at the external data pin to a corresponding input/output line. The corresponding input/output line is selected in response to bit values of a set of bits included in the received data.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: October 20, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun Hee Shin, Young Man Ahn, Seung Mo Jung, You Keun Han, Sang Jhun Hwang
  • Patent number: 9099166
    Abstract: A memory module comprises a plurality of semiconductor memory devices each comprising a mode register set (MRS) circuit configured to generate an enable signal corresponding to an error mode of the semiconductor memory device in response to an MRS command received from a command decoder, and an address buffer configured to store a predetermined address signal, to receive an address signal and corresponding data from an external device, and to compare the address signal received with the predetermined address signal in response to the enable signal. As a consequence of determining that the address signal received from the external device is the same as the predetermined address signal stored in the address buffer, data different from the corresponding data received from the external device is written to a memory cell corresponding to the predetermined address signal.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: August 4, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun Hee Shin, Won Hyung Song, Jong Min Lee, You Keun Han
  • Publication number: 20140219044
    Abstract: A memory module comprises a plurality of semiconductor memory devices each comprising a mode register set (MRS) circuit configured to generate an enable signal corresponding to an error mode of the semiconductor memory device in response to an MRS command received from a command decoder, and an address buffer configured to store a predetermined address signal, to receive an address signal and corresponding data from an external device, and to compare the address signal received with the predetermined address signal in response to the enable signal. As a consequence of determining that the address signal received from the external device is the same as the predetermined address signal stored in the address buffer, data different from the corresponding data received from the external device is written to a memory cell corresponding to the predetermined address signal.
    Type: Application
    Filed: January 16, 2014
    Publication date: August 7, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: JUN HEE SHIN, WON HYUNG SONG, JONG MIN LEE, YOU KEUN HAN
  • Publication number: 20140043920
    Abstract: A memory device includes a memory cell array and a data input/output circuit. The memory cell array includes a plurality of memory cells connected to a plurality of bit lines and a plurality of word lines. The data input/output circuit is configured to receive data from external data pins of the memory device, output the received data to the memory cell array through a plurality of input/output lines electrically coupled to the plurality of bit lines, receive data read from the memory cell array through the plurality of input/output lines, and output the read data through the external data pins. For each external data pin, the data input/output circuit is configured to output data received at the external data pin to a corresponding input/output line. The corresponding input/output line is selected in response to bit values of a set of bits included in the received data.
    Type: Application
    Filed: August 8, 2013
    Publication date: February 13, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jun Hee SHIN, Young Man AHN, Seung Mo JUNG, You Keun HAN, Sang Jhun HWANG