Abstract: A light emitting display device includes a display panel. The display panel includes a display region where pixels are arranged, a non-display region outside the display region, and a folding region extending along a direction. The display device includes a strain sensor located in the folding region in the non-display region and having a Wheatstone bridge circuit structure. The display device includes a gamma reference voltage portion providing an input voltage to the strain sensor. The display device includes a power supply portion providing a reference voltage to the gamma reference voltage portion. The display device includes a controller receiving an output voltage of the strain sensor.

Abstract: A semiconductor device may include a gate structure, a plurality of channel patterns spaced apart from each other in a first direction, each of the plurality of channel patterns extending through the gate structure in a second direction substantially perpendicular to the first direction, a source/drain layer adjacent to the gate structure in the second direction, the source/drain layer contacting the plurality of channel patterns, a first spacer on a sidewall of the gate structure in the second direction and including an insulating material, and a second spacer on a sidewall of the first spacer in the second direction, the second spacer contacting the source/drain layer. The first spacer may include opposite edge portions in the first direction and a center portion in the first direction, and a width of the first spacer in the second direction may increase from the opposite edge portions toward the center portion.

Abstract: A light emitting display device is disclosed that includes a substrate, a transistor, an insulating layer, a pixel electrode, a pixel defining layer, a spacer, and a protective layer. The transistor is positioned on the substrate and the insulating layer is positioned on the transistor. The pixel electrode is positioned on the insulating layer and electrically connected to the transistor. The pixel defining layer is positioned on the insulating layer and has an opening overlapping the pixel electrode. The spacer is positioned on the pixel defining layer and the protective layer is positioned on the spacer. The protective layer includes a first layer positioned on the spacer and a second layer positioned on the first layer.

Abstract: Provided are a display apparatus in which a defect rate is reduced and an electronic device including the same. The display apparatus includes a substrate, a first pixel electrode and a second pixel electrode, which are disposed on the substrate, a pixel-defining layer disposed on the substrate and covering edges of the first pixel electrode and second pixel electrode, and a spacer disposed on the pixel-defining layer and provided between the first pixel electrode and the second pixel electrode in a plan view. The pixel-defining layer includes at least one trench provided between the spacer and the first pixel electrode in a plan view and an angle between an inner surface of the at least one trench and a bottom surface of the at least one trench is more than 90°.

Abstract: A display apparatus includes: a display panel including a plurality of data lines and a plurality of pixels respectively connected to the plurality of data lines; a first data driving portion including a plurality of channels respectively connected to one ends of the plurality of data lines and a plurality of first output buffers which are respectively arranged at the plurality of channels; and a second data driving portion including a plurality of channels respectively connected to the other ends of the plurality of data lines and a plurality of second output buffers which are respectively arranged at the plurality of channels, wherein each of the first and second output buffers is alternately in a positive (+) chopping state and a negative (?) chopping state by frame, and wherein offset directions of output voltages of the first and second output buffers at the corresponding channel are the same in the same frame.

Abstract: The disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate. A method performed by an apparatus of a wireless communication system is provided. The method includes receiving, from a base station, first information related to interference among a plurality of user equipments (UEs) that are to receive a resource allocation, second information related to a number of available resources, and third information related to a resource allocation reward associated with each of the plurality of user equipments (UEs), selecting a plurality of qubits based on the first information and the second information, and generating, based on the third information, resource allocation information derived from the plurality of qubits, where the resource allocation to the plurality of UEs is based on the resource allocation information.

Abstract: A light emitting display device includes a display panel. The display panel includes a display region where pixels are arranged, a non-display region outside the display region, and a folding region extending along a direction. The display device includes a strain sensor located in the folding region in the non-display region and having a Wheatstone bridge circuit structure. The display device includes a gamma reference voltage portion providing an input voltage to the strain sensor. The display device includes a power supply portion providing a reference voltage to the gamma reference voltage portion. The display device includes a controller receiving an output voltage of the strain sensor.

Abstract: A flexible display apparatus includes: a first flexible substrate including carbon and having an upper surface, a lower surface facing the upper surface, and a lateral surface coupling the upper surface to the lower surface; a first barrier layer on the first flexible substrate to cover the first flexible substrate; a second flexible substrate on the first barrier layer, the second flexible substrate including carbon and having an upper surface, a lower surface facing the upper surface, and a lateral surface coupling the upper surface to the lower surface; and an organic light emitting device on the second flexible substrate.

Abstract: A method of predicting acoustic performance of a porous polymer material includes measuring initial properties of the polymer material including non-acoustic properties and mechanical properties, calculating properties after deterioration by inputting the initial properties into a deterioration model, and calculating acoustic performance after deterioration of the polymer material by inputting the properties after deterioration into an acoustic model, in order to enable acoustic performance of the polymer material deteriorated by time and temperature to be predicted with high accuracy.

Abstract: A display apparatus includes: a display panel including a plurality of data lines and a plurality of pixels; first and second data driving portions including a plurality of first and second data ICs; a timing control portion providing input first and second lock signals to the first and second data driving portions, respectively; and a comparison circuit receiving output first and second lock signals generated from the first and second data driving portions according to the input first and second lock signals, respectively, and comparing and synchronizing the output first and second lock signals to provide a synchronous lock signal to the timing control portion, wherein in a lock state of the synchronous lock signal, the timing control portion transmits image data to the first and second data driving portions, and the first and second data driving portions output respective data voltages.

Abstract: A display apparatus includes: a display panel including a plurality of data lines and a plurality of pixels respectively connected to the plurality of data lines; a first data driving portion including a plurality of channels respectively connected to one ends of the plurality of data lines and a plurality of first output buffers which are respectively arranged at the plurality of channels; and a second data driving portion including a plurality of channels respectively connected to the other ends of the plurality of data lines and a plurality of second output buffers which are respectively arranged at the plurality of channels, wherein each of the first and second output buffers is alternately in a positive (+) chopping state and a negative (?) chopping state by frame, and wherein offset directions of output voltages of the first and second output buffers at the corresponding channel are the same in the same frame.

Abstract: Disclosed is a display device in which a gap size between bonding pads disposed on a circuit film is increased even though the number of signal lines for driving high-resolution and high-frequency display and the number of power lines for low-speed operation increase. The display device includes a display panel; a printed circuit board; and a circuit film disposed between and connected to the display panel and the printed circuit board, wherein the circuit film includes an input side bonding area connected to the printed circuit board and an output side bonding area connected to the display panel, wherein the input side bonding area includes a plurality of input pads connected to the output side bonding area, wherein the plurality of input pads are arranged in two rows.

Abstract: The present invention relates to a technology for addressing resource allocation problems by solving the graph multi-coloring problem on a noisy intermediate-scale quantum (NISQ)-based quantum computer using a quantum approximate optimization algorithm (QAOA). A method of operation of a graph multi-coloring problem solving apparatus operated by a processor is provided.

Abstract: The present disclosure relates to quantum approximate optimization technology, and more particularly, to an apparatus and method for an improved quantum approximate optimization algorithm. In one embodiment, the disclosure describes a method for implementing a quantum approximate optimization algorithm, which is performed by a processor of a quantum computing device.

Abstract: The present invention relates to a device for virtually simulating a quantum communication circuit.

Abstract: Disclosed is a method for a logical operation performed by a quantum computing device, which may include: acquiring a logical qubit in which a physical qubit is encoded with a surface code; when performing a logical Hadamard operation in the logical qubit, and performing a first operation using a first joint measurement, performing a boundary flip; performing the first operation by using a second joint measurement other than the first joint measurement in the boundary-flipped logical qubit; and changing an order of the logical Hadamard operation after a step of performing the first operation by using the second joint measurement.

Abstract: Disclosed is a method for a logical operation performed by a quantum computing device, which may include: placing a data patch in which information is stored and computed, and a first ancilla patch which is consumed during a logical operation at a predetermined first interval; placing a first logical ancilla qubit between the data patch and the first ancilla patch; placing a second logical ancilla qubit to have a predetermined distance from one side of the first ancilla patch; and performing a joint measurement utilizing the data patch and the first ancilla patch.

Abstract: The present disclosure relates to a quantum error correction code and, more particularly, to a method and apparatus for optimizing a quantum error correction code in biased error environment. The method for optimizing a quantum error correction code, according to an embodiment of the present disclosure, may comprise the steps of: estimating, on the basis of a physical error rate (pphy) and a bias degree (?), a logical error rate (Pfail) for each of one or more candidate lattice sizes; determining, on the basis of the estimated logical error rate (Pfail) and a target logical error rate (Pf,target), an optimal lattice size from among the one or more candidate lattice sizes; and arranging a Qubit on the basis of the optimal lattice size. Here, when the bias degree (?) exceeds 1, the one or more candidate lattice sizes may be defined in the form of a rectangular excluding a square.

Abstract: The present invention relates to a method and apparatus for performing position estimation of multiple receiving coil and wireless power transmission. A method for performing wireless power transmission according to an embodiment of the present disclosure may comprise: calculating a current value flowing through one or more transmitting (Tx) coils by measuring an impedance value of the one or more Tx coils; identifying whether a receiving (Rx) coil associated with the one or more Tx coils exists; when one or more Rx coils exist, calculating a correlation value between a Tx coil and a Rx coil for each of the one or more Rx coils; determining a position of the one or more Rx coils; and performing wireless power transmission to the one or more Rx coils.

Abstract: A light emitting display device includes a display panel. The display panel includes a display region where pixels are arranged, a non-display region outside the display region, and a folding region extending along a direction. The display device includes a strain sensor located in the folding region in the non-display region and having a Wheatstone bridge circuit structure. The display device includes a gamma reference voltage portion providing an input voltage to the strain sensor. The display device includes a power supply portion providing a reference voltage to the gamma reference voltage portion. The display device includes a controller receiving an output voltage of the strain sensor.