Patents by Inventor Jun-Heyoung Park

Jun-Heyoung Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10847474
    Abstract: A semiconductor package includes a connection structure including one or more redistribution layers, a semiconductor chip disposed on the connection structure and electrically connected to the one or more redistribution layers, an encapsulant disposed on the connection structure and covering at least a portion of the semiconductor chip, and a shielding structure covering at least a portion of the encapsulant. The shielding structure includes a conductive pattern layer having a plurality of openings, a first metal layer covering the conductive pattern layer and extending across the plurality of openings, and a second metal layer covering the first metal layer. The second metal layer has a thickness greater than a thickness of the first metal layer.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: November 24, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Woon Chun Kim, Jun Heyoung Park, Ji Hye Shim, Sung Keun Park, Gun Lee
  • Patent number: 10790255
    Abstract: A fan-out semiconductor package includes a frame comprising a plurality of wiring layers electrically connected to one another, and having a recessed portion having a stopper layer 112aM disposed on a bottom surface of the recessed portion, and a through-hole penetrating through the stopper layer; a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, and disposed in the recessed portion such that the inactive surface opposes the stopper layer; an encapsulant covering at least portions of the frame and the inactive surface of the semiconductor chip, and filling at least a portion of the recessed portion; and an interconnect structure disposed on the frame and the active surface of the semiconductor chip, and comprising a redistribution layer electrically connected to the plurality of wiring layers and the connection pad.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: September 29, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Woon Chun Kim, Jun Heyoung Park, Ji Hye Shim, Sung Keun Park, Gun Lee
  • Publication number: 20200152580
    Abstract: A semiconductor package includes a connection structure including one or more redistribution layers, a semiconductor chip disposed on the connection structure and electrically connected to the one or more redistribution layers, an encapsulant disposed on the connection structure and covering at least a portion of the semiconductor chip, and a shielding structure covering at least a portion of the encapsulant. The shielding structure includes a conductive pattern layer having a plurality of openings, a first metal layer covering the conductive pattern layer and extending across the plurality of openings, and a second metal layer covering the first metal layer. The second metal layer has a thickness greater than a thickness of the first metal layer.
    Type: Application
    Filed: May 6, 2019
    Publication date: May 14, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Woon Chun KIM, Jun Heyoung PARK, Ji Hye SHIM, Sung Keun PARK, Gun LEE
  • Publication number: 20200105703
    Abstract: A fan-out semiconductor package includes a frame comprising a plurality of wiring layers electrically connected to one another, and having a recessed portion having a stopper layer 112aM disposed on a bottom surface of the recessed portion, and a through-hole penetrating through the stopper layer; a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, and disposed in the recessed portion such that the inactive surface opposes the stopper layer; an encapsulant covering at least portions of the frame and the inactive surface of the semiconductor chip, and filling at least a portion of the recessed portion; and an interconnect structure disposed on the frame and the active surface of the semiconductor chip, and comprising a redistribution layer electrically connected to the plurality of wiring layers and the connection pad.
    Type: Application
    Filed: March 4, 2019
    Publication date: April 2, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Woon Chun Kim, Jun Heyoung Park, Ji Hye Shim, Sung Keun Park, Gun Lee
  • Publication number: 20190371737
    Abstract: An electromagnetic interference shielding structure includes a base layer and an electromagnetic interference shielding layer disposed on the base layer. The electromagnetic shielding layer includes a plurality of porous conductor layers, each of the porous conductor layers has a plurality of openings, and the porous conductor layers are stacked on each other in a stacking direction. A semiconductor package includes the electromagnetic interference shielding structure.
    Type: Application
    Filed: October 16, 2018
    Publication date: December 5, 2019
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Woon Chun KIM, Ji Hye SHIM, Jun Heyoung PARK
  • Patent number: 8377748
    Abstract: A method of manufacturing a cooling fin and package substrate that includes preparing a mold, which has a support base and a resin layer formed on the support base and including on a side thereof a groove, which is configured to form a cooling fin; printing fireable paste containing a carbon component on a side of the mold that has the groove configured to form a cooling fin; removing the support base to leave a cooling object; and firing the cooling object.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: February 19, 2013
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Eung Suek Lee, Je Gwang Yoo, Chang Sup Ryu, Jun Oh Hwang, Jun Heyoung Park, Jee Soo Mok
  • Patent number: 8222534
    Abstract: A printed circuit board and a method of manufacturing the printed circuit board are disclosed. The method of manufacturing a printed circuit board, by forming at least one bump for interlayer conduction on a surface of a board and stacking an insulation layer on the surface of the board, can include the operations of forming at least one dam on the surface of the board that surrounds a region corresponding to the bump, forming the bump by printing conductive paste onto the region corresponding to the bump, and stacking the insulation layer onto the surface of the board. This method can be utilized to improve productivity and resolve the problem of spreading.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: July 17, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jun-Heyoung Park, Jee-Soo Mok, Ki-Hwan Kim, Sung-Yong Kim
  • Publication number: 20120175162
    Abstract: A printed circuit board having an insulating layer; circuit patterns formed on both surfaces of the insulating layer in order to be embedded in the insulating layer; and a bump formed to pass through the insulating layer in order to electrically connect the circuit patterns formed on both surfaces of the insulating layer.
    Type: Application
    Filed: March 23, 2012
    Publication date: July 12, 2012
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jee Soo MOK, Jun Heyoung PARK
  • Publication number: 20120168205
    Abstract: A printed circuit board and a method for manufacturing the printed circuit board are disclosed. The method can include; providing an insulated layer, in which a first metal layer is formed on one side of the insulated layer; forming a groove on the insulated layer; forming a metallic substance on an inner side of the groove and on another side of the insulated layer; and forming a first circuit pattern on at least one of one side of the insulated layer and the metallic substance formed on the groove by removing a portion of the first metal layer. The present invention provides the printed circuit board having a high efficiency of heat emission by disposing a heat sink in direct contact with a board and the method of manufacturing the printed circuit board.
    Type: Application
    Filed: March 16, 2012
    Publication date: July 5, 2012
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jun-Oh HWANG, Jee-Soo Mok, Jun-Heyoung Park, Kyung-Ah Lee, Eung-Suek Lee
  • Patent number: 8166647
    Abstract: A printed circuit board and a method for manufacturing the printed circuit board are disclosed. The method can include; providing an insulated layer, in which a first metal layer is formed on one side of the insulated layer; forming a groove on the insulated layer; forming a metallic substance on an inner side of the groove and on another side of the insulated layer; and forming a first circuit pattern on at least one of one side of the insulated layer and the metallic substance formed on the groove by removing a portion of the first metal layer. The present invention provides the printed circuit board having a high efficiency of heat emission by disposing a heat sink in direct contact with a board and the method of manufacturing the printed circuit board.
    Type: Grant
    Filed: January 12, 2009
    Date of Patent: May 1, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jun-Oh Hwang, Jee-Soo Mok, Jun-Heyoung Park, Kyung-Ah Lee, Eung-Suek Lee
  • Patent number: 8161634
    Abstract: A method of fabricating a printed circuit, which involves forming a bump on a first metal layer; laminating an insulating layer on the bump so that the bumps passes through the insulating layer; placing a second metal layer on the insulating layer and then conducting heating and pressing, thus laminating the second metal layer on the insulating layer; etching the first metal layer and the second metal layer, thus forming circuit patterns on both surfaces of the insulating layer; and heating and pressing both surfaces of the insulating layer, thus embedding the circuit patterns in the insulating layer, such that the circuit pattern is embedded in an insulating layer to decrease the thickness of a printed circuit board, and the time and cost required for the process of fabricating a printed circuit board are decreased.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: April 24, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jee Soo Mok, Jun Heyoung Park
  • Publication number: 20120080401
    Abstract: A method of fabricating a multilayer printed circuit board includes preparing a first substrate, and preparing a second substrate, in parallel to the formation of the first substrate, that is, at the same time of the formation of the first substrate, by forming a third inner circuit pattern on one surface of a third insulating layer and forming a window on the other surface of the third insulating layer.
    Type: Application
    Filed: December 12, 2011
    Publication date: April 5, 2012
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jee Soo MOK, Jun Heyoung Park, Ki Hwan Kim, Sung Yong Kim
  • Publication number: 20110308069
    Abstract: A method of manufacturing a cooling fin and package substrate that includes preparing a mold, which has a support base and a resin layer formed on the support base and including on a side thereof a groove, which is configured to form a cooling fin; printing fireable paste containing a carbon component on a side of the mold that has the groove configured to form a cooling fin; removing the support base to leave a cooling object; and firing the cooling object.
    Type: Application
    Filed: September 1, 2011
    Publication date: December 22, 2011
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Eung Suek LEE, Je Gwang YOO, Chang Sup RYU, Jun Oh HWANG, Jun Heyoung PARK, Jee Soo MOK
  • Patent number: 8065798
    Abstract: A fabrication method which can improve electrical properties, shorten processing time, and reduce the thickness of a chip package by achieving an ultra-thin fine circuit pattern. The method for fabricating a printed circuit board includes: providing an insulating material; forming in the insulating material at least one via-hole for interlayer electrical connection; ion beam treating the surface of the insulating material having the via-hole formed therein; forming a copper seed layer on the surface-treated insulating material using a vacuum deposition process; and plating a copper pattern on the copper seed layer to form a circuit pattern.
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: November 29, 2011
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Dong Sun Kim, Taehoon Kim, Jong Seok Song, Sam Jin Her, Jun Heyoung Park
  • Patent number: 8058558
    Abstract: A printed circuit board and a manufacturing method thereof are disclosed. Using a method of manufacturing a printed circuit board which includes forming a circuit pattern, which includes lands, on a first board; forming a paste bump on the land of the first board; and stacking an insulation on a surface of the first board such that the paste bump penetrates the insulation, where the paste bump is formed to cover the land of the first board, the areas of the lands can be reduced to manufacture a printed circuit board of high density, and the contact reliability can be increased due to the increase in contact area between the lands and paste bumps to improve the performance of the high-density printed circuit-board.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: November 15, 2011
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jee-Soo Mok, Dong-Jin Park, Jun-Heyoung Park, Ki-Hwan Kim, Sung-Young Kim
  • Publication number: 20110099807
    Abstract: A fabrication method which can improve electrical properties, shorten processing time, and reduce the thickness of a chip package by achieving an ultra-thin fine circuit pattern. The method for fabricating a printed circuit board includes: providing an insulating material; forming in the insulating material at least one via-hole for interlayer electrical connection; ion beam treating the surface of the insulating material having the via-hole formed therein; forming a copper seed layer on the surface-treated insulating material using a vacuum deposition process; and plating a copper pattern on the copper seed layer to form a circuit pattern.
    Type: Application
    Filed: July 22, 2010
    Publication date: May 5, 2011
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Dong Sun Kim, Taehoon Kim, Jong Seok Song, Sam Jin Her, Jun Heyoung Park
  • Patent number: 7841074
    Abstract: A method of fabricating a paste bump for a printed circuit board, provides preparing a base plate; printing a conductive paste on the base plate and drying the conductive paste on the base plate, thus forming a first paste bump; flattening an upper surface of the first paste bump through coining; and printing a conductive paste on the first paste bump and drying the conductive paste on the first bump, thus forming a second paste bump, wherein the printing a conductive paste on the base plate and drying the conductive paste on the base plate includes placing a first mask having a hole having a first size on the base plate; applying a conductive paste on the first mask, and pressing the conductive paste using a squeegee; filling the hole having a first size in the first mask with the conductive paste, and sticking a bottom of the conductive paste to the base plate; and removing the first mask and drying the conductive paste, thus forming the first paste bump.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: November 30, 2010
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jee Soo Mok, Jun Heyoung Park, Ki Hwan Kim, Sung Yong Kim, Sang Hyun Park
  • Patent number: 7836590
    Abstract: A manufacturing method for a printed circuit board is disclosed. The method includes: forming a first circuit pattern on a metal layer of a conductive carrier, which has the metal layer stacked on one side, pressing the conductive carrier and a first insulation layer together with the first circuit pattern facing the first insulation layer, forming a via by selectively removing the conductive carrier, and removing the metal layer. Using this method, a high-density thin package can be manufactured with increased reliability, and the productivity of the manufacturing process can also be improved.
    Type: Grant
    Filed: February 1, 2008
    Date of Patent: November 23, 2010
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jee-Soo Mok, Jun-Heyoung Park
  • Patent number: 7794820
    Abstract: Disclosed herein are a printed circuit board and a fabrication method thereof, which can improve electrical properties, shorten processing time, and reduce the thickness of a chip package by achieving an ultra-thin fine circuit pattern. The printed circuit board includes an insulating material; a via-hole formed in a given location of the insulating material; a copper seed layer formed through ion beam surface treatment and vacuum deposition on the surface of the insulating material having the via-hole formed therein; and a copper pattern plating layer formed on a given region of the insulating material, which has the copper seed layer formed thereon, and in the via-hole.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: September 14, 2010
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Dong Sun Kim, Taehoon Kim, Jong Seok Song, Sam Jin Her, Jun Heyoung Park
  • Patent number: 7653991
    Abstract: A method for manufacturing a printed circuit board having an embedded component is disclosed. The method includes: forming at least one contact bump and at least one electrode bump on one side of a base substrate; mounting the component such that the electrode bump is in correspondence with a contact terminal of the component; stacking an insulation layer, in which an opening is formed in correspondence to the component, on the one side of the base substrate, such that the contact bump penetrates the insulation layer; filling a filler in the opening; and stacking a metal layer on the insulation layer. Using the method, the reliability of circuit connections between the component and the circuit patterns can be improved, and the manufacturing process can be reduced in embedding the component in the printed circuit board.
    Type: Grant
    Filed: January 8, 2008
    Date of Patent: February 2, 2010
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jee-Soo Mok, Jun-Heyoung Park, Ki-Hwan Kim, Sung-Yong Kim