Patents by Inventor Jun Hirokawa

Jun Hirokawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5519658
    Abstract: Disclosed are a semiconductor integrated circuit device and methods for production thereof. An embodiment of the invention is a semiconductor chip that comprises fuses constituting part of redundancy circuits formed therein, the fuses being made of the same ingredients CCB bump substrate metal. The fuses are patterned simultaneously during the patterning of the CCB bump substrate metal. This involves forming the fuses using at least part of the ingredients of an electrode conductor pattern in the chip. The cutting regions of the fuses are made of only one of the metal layers constituting the substrate. The principal plane of the semiconductor chip has a fuse protective film formed over at least the cutting regions of the fuses for protection of the latter. In operation, a switch MOSFET under switching control of a redundancy signal is used to select one of two transmission paths, one carrying an address signal or a decode signal, the other carrying a reference voltage.
    Type: Grant
    Filed: November 1, 1994
    Date of Patent: May 21, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Takayuki Uda, Toshiro Hiramoto, Nobuo Tamba, Hisashi Ishida, Kazuhiro Akimoto, Masanori Odaka, Tasuku Tanaka, Jun Hirokawa, Masayuki Ohayashi
  • Patent number: 5360988
    Abstract: Disclosed are a semiconductor integrated circuit device and methods for production thereof. An embodiment of the invention is a semiconductor chip that comprises fuses constituting part of redundancy circuits formed therein, the fuses being made of the same ingredients as those of a CCB bump substrate metal. The fuses are patterned simultaneously during the patterning of the CCB bump substrate metal. This involves forming the fuses using at least part of the ingredients of an electrode conductor pattern in the chip. The cutting regions of the fuses are made of only one of the metal layers constituting the substrate. The principal plane of the semiconductor chip has a fuse protective film formed over at least the cutting regions of the fuses for protection of the latter. In operation, a switch MOSFET under switching control of a redundancy signal is used to select one of two transmission paths, one carrying an address signal or a decode signal, the other carrying a reference voltage.
    Type: Grant
    Filed: June 23, 1992
    Date of Patent: November 1, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Takayuki Uda, Toshiro Hiramoto, Nobuo Tamba, Hisashi Ishida, Kazuhiro Akimoto, Masanori Odaka, Tasuku Tanaka, Jun Hirokawa, Masayuki Ohayashi
  • Patent number: 4995765
    Abstract: A sanitary waste collection system and a method therefor which enable the free disposal of waste at various places in a building, and saves labor required for carrying and collecting the waste. The waste collection system includes charge ports provided at every floor of the building into which are thrown waste stored in waste containers of a certain configuration, vertical transport tubes connected to each floor of the building as well as charge ports, horizontal transport tubes connected to the lower ends of the vertical transport tubes and extending to a waste accumulation area, and an air blowing mechanism for force-feeding air in the horizontal transport tubes, with the diameters of the vertical and horizontal transport tubes and being a little larger than the outer diameter of the waste container in section.
    Type: Grant
    Filed: April 18, 1988
    Date of Patent: February 26, 1991
    Assignees: Shimizu Construction Co., Ltd., Shinmeiwa Industry Co., Ltd.
    Inventors: Tomoya Tokuhiro, Nobutaka Koibuchi, Teruhiko Miyauchi, Koshin Kikuchi, Jun Hirokawa, Kunio Yamashiro, Sakae Nishizuka, Ippei Watanabe, Shozo Maruo, Yohichiro Tsutsui, Sadahito Ishikawa