Abstract: Disclosed are methods and apparatus for bit packing data having various bit widths in a computer system. The methods and apparatus utilize a fixed bit packing or unpacking network that is configured to pack or unpack data bits of a number of different bit widths from a first number of bit locations to a second number of bit locations in the computer system. The network is specifically configured to pack bits stored in a same bit slot position in respective bit locations of the first number of bit locations by routing the bits into bit slots of a same bit location in the second number of bit locations to form bit bundles in respective ones of the second number of bit locations. Use of a fixed packing network affords optimal matching of bit width to an application that minimizes cost, area, and power, as well as decreasing or minimizing latency.

Abstract: Systems and methods for performing on-the-fly format conversion on data vectors during load/store operations are described herein. In one embodiment, a method for loading a data vector from a memory into a vector unit comprises reading a plurality of samples from the memory, wherein the plurality of samples are packed in the memory. The method also comprises unpacking the samples to obtain a plurality of unpacked samples, performing format conversion on the unpacked samples in parallel, and sending at least a portion of the format-converted samples to the vector unit.

Abstract: Various aspects of this disclosure describe a bi-directional, dual interconnect bus configured in a ring to route data to processors implementing modem functions. A plurality of nodes may be coupled to form a ring bus comprising at least two interconnect rings. A plurality of processors may be assigned to the plurality of nodes. A first processor among the plurality of processors may be configured to process a first data type, and a second processor among the plurality of processors may be configured to process a second data type. Data on the ring bus may be separated into the first data type and the second data type, and separated data of the first data type may be routed on one interconnect ring to the first processor and separated data of the second data type may be routed on another interconnect ring to the second processor.

Abstract: Systems and methods for performing on-the-fly format conversion on data vectors during load/store operations are described herein. In one embodiment, a method for loading a data vector from a memory into a vector unit comprises reading a plurality of samples from the memory, wherein the plurality of samples are packed in the memory. The method also comprises unpacking the samples to obtain a plurality of unpacked samples, performing format conversion on the unpacked samples in parallel, and sending at least a portion of the format-converted samples to the vector unit.

Abstract: A digital signal processor having an ALU and accumulating register small in bit number. The digital signal processor adds r-bit rounding bits to an N-bit data(wherein r<N) and adds g-bit guard bits to the high-order bits of the data using bit alignment units each being implemented with a wiring, when N bit data is processed. The data added by the guard bits and the rounding bits is operated by means of the accumulator. The operated data is selectively rounded by a rounding processor. Also, the selectively rounded data is selectively saturated by a saturation processor.