Abstract: A voltage generating circuit includes a voltage supplying circuit and a current biasing circuit. The voltage supplying circuit is configured to supply a first power voltage to an output node based on a first enable signal. The current biasing circuit is configured to control a bias current to flow from the output node based on a second enable signal. The second enable signal is enabled after the first enable signal is enabled.

Abstract: A nonvolatile memory apparatus performs a plurality of read operations by using a plurality of read voltages. A first read operation is performed by applying a first read voltage to a memory cell. A second read operation is selectively performed based on whether a snap-back of the memory cell occurs during the first read operation. The second read operation is performed by applying a second read voltage having a higher voltage level than the first read voltage to the memory cell.

Abstract: A voltage generating circuit includes a voltage supplying circuit and a current biasing circuit. The voltage supplying circuit is configured to supply a first power voltage to an output node based on a first enable signal. The current biasing circuit is configured to control a bias current to flow from the output node based on a second enable signal. The second enable signal is enabled after the first enable signal is enabled.

Abstract: A nonvolatile memory apparatus may include a memory cell, a bit line control circuit, and a word line control circuit. The memory cell may be coupled between a global bit line and a global word line. During a read operation, the bit line control circuit may provide a first high voltage to the global bit line and provide a second high voltage to the global bit line when snapback of the memory cell occurs. During the read operation, the word line control circuit may provide a second read supply voltage to the global word line and provide an anneal supply voltage to the global word line when snapback of the memory cell occurs.

Abstract: A voltage generating circuit includes a voltage supplying circuit and a current biasing circuit. The voltage supplying circuit is configured to supply a first power voltage to an output node based on a first enable signal. The current biasing circuit is configured to control a bias current to flow from the output node based on a second enable signal. The second enable signal is enabled after the first enable signal is enabled.

Abstract: A nonvolatile memory apparatus may include a memory cell, a bit line control circuit, and a word line control circuit. The memory cell may be coupled between a global bit line and a global word line. During a read operation, the bit line control circuit may provide a first high voltage to the global bit line and provide a second high voltage to the global bit line when snapback of the memory cell occurs. During the read operation, the word line control circuit may provide a second read supply voltage to the global word line and provide an anneal supply voltage to the global word line when snapback of the memory cell occurs.

Abstract: A voltage generating circuit includes a voltage supplying circuit and a current biasing circuit. The voltage supplying circuit is configured to supply a first power voltage to an output node based on a first enable signal. The current biasing circuit is configured to control a bias current to flow from the output node based on a second enable signal. The second enable signal is enabled after the first enable signal is enabled.

Abstract: A nonvolatile memory apparatus performs a plurality of read operations by using a plurality of read voltages. A first read operation is performed by applying a first read voltage to a memory cell. A second read operation is selectively performed based on whether a snap-back of the memory cell occurs during the first read operation. The second read operation is performed by applying a second read voltage having a higher voltage level than the first read voltage to the memory cell.

Abstract: A nonvolatile memory apparatus performs a plurality of read operations by using a plurality of read voltages. A first read operation is performed by applying a first read voltage to a memory cell. A second read operation is selectively performed based on whether a snap-back of the memory cell occurs during the first read operation. The second read operation is performed by applying a second read voltage having a higher voltage level than the first read voltage to the memory cell.

Abstract: A nonvolatile memory apparatus may include a memory cell, a bit line control circuit, and a word line control circuit. The memory cell may be coupled between a global bit line and a global word line. During a read operation, the bit line control circuit may provide a first high voltage to the global bit line and provide a second high voltage to the global bit line when snapback of the memory cell occurs. During the read operation, the word line control circuit may provide a second read supply voltage to the global word line and provide an anneal supply voltage to the global word line when snapback of the memory cell occurs.

Abstract: A nonvolatile memory apparatus performs a plurality of read operations by using a plurality of read voltages. A first read operation is performed by applying a first read voltage to a memory cell. A second read operation is selectively performed based on whether a snap-back of the memory cell occurs during the first read operation. The second read operation is performed by applying a second read voltage having a higher voltage level than the first read voltage to the memory cell.

Abstract: A non-volatile memory apparatus may include a program current generation circuit, a clamping circuit and a voltage generation circuit. The program current generation circuit may increase a program current based on a memory cell current flowing through a memory cell. The clamping circuit may clamp the memory cell current. The voltage generation circuit may apply a voltage corresponding to a verification-write voltage to the memory cell. Therefore, the verification-write operation may be performed to the memory cell.

Abstract: A phase change memory device may include a plurality of word lines, a plurality of bit lines, a phase change memory cell, and a discharging circuit. The word lines and the bit lines may intersect each other. The phase change memory cell may be positioned at an intersection point between the word lines and the bit lines. The discharging circuit may be configured to apply a ground voltage to a non-selected word line adjacent to a selected word line or a non-selected bit line adjacent to a selected bit line.

Abstract: A non-volatile memory apparatus may include a program current generation circuit, a clamping circuit and a voltage generation circuit. The program current generation circuit may increase a program current based on a memory cell current flowing through a memory cell. The clamping circuit may clamp the memory cell current. The voltage generation circuit may apply a voltage corresponding to a verification-write voltage to the memory cell. Therefore, the verification-write operation may be performed to the memory cell.

Abstract: A system for tracking a subject moving within a space using stereo cameras includes stereo cameras installed in different directions, a space data composition unit forming a space map where information about 3D space is shared by matching depth maps generated in photographing areas of the stereo cameras, a subject sensing unit analyzing point clouds or the space map and determining that the subject is present in a photographing area of a stereo camera corresponding to a point, a PTZ camera moving so that a photographing direction is directed toward the subject, and a driving control unit driving the PTZ camera using a first method for setting an initial value and for driving the PTZ camera and/or a second method for setting the photographing zones of the 3D space, presetting the driving values of the PTZ camera, fetching the preset value of the zone, and driving the PTZ camera.

Abstract: A semiconductor memory apparatus, including a first mat which includes a first bit line and a first word line and a second mat which includes a second bit line and a second word line, includes a first bit line driving circuit configured to enable the first bit line in response to a first bit line select signal and a first machine bit line select signal; a second bit line driving circuit configured to enable the second bit line in response to a second bit line select signal and a second machine bit line select signal; a column-related decoding circuit configured to selectively enable the first and second bit line select signals in response to a column address; and a state machine configured to selectively enable the first and second machine bit line select signals in response to the column address.

Abstract: A semiconductor memory apparatus, including a first mat which includes a first bit line and a first word line and a second mat which includes a second bit line and a second word line, includes a first bit line driving circuit configured to enable the first bit line in response to a first bit line select signal and a first machine bit line select signal; a second bit line driving circuit configured to enable the second bit line in response to a second bit line select signal and a second machine bit line select signal; a column-related decoding circuit configured to selectively enable the first and second bit line select signals in response to a column address; and a state machine configured to selectively enable the first and second machine bit line select signals in response to the column address.

Abstract: A phase change memory device may include a plurality of word lines, a plurality of bit lines, a phase change memory cell, and a discharging circuit. The word lines and the bit lines may intersect each other. The phase change memory cell may be positioned at an intersection point between the word lines and the bit lines. The discharging circuit may be configured to apply a ground voltage to a non-selected word line adjacent to a selected word line or a non-selected bit line adjacent to a selected bit line.

Abstract: A resistance variable memory apparatus may include a memory cell array and a controller. The memory cell array may include a plurality of resistance variable memory cells. The controller may control a current path flowing through any one memory cell and a current path flowing through the other memory cell to be formed differently from each other in response to at least two address signals.

Abstract: An analog capacitor is disclosed. The analog capacitor may include a main analog capacitor, an interlayer insulating layer, and a plurality of stacked sub analog capacitors. The main analog capacitor may be formed over a semiconductor substrate. The interlayer insulating layer may be interposed between the semiconductor substrate and the main analog capacitor. The plurality of stacked sub analog capacitors may be inserted into the interlayer insulating layer.