Abstract: A memory apparatus includes a first switch and a second switch configured to electrically connect or disconnect a first voltage line and a bit line in response to a first driving signal and a second driving signal; a third switch and a fourth switch configured to electrically connect or disconnect a second voltage line and a word line in response to a third driving signal and a fourth driving signal; a memory cell electrically connected between the bit line and the word line; and a signal level control circuit configured to differentially control turn-on degrees of the third and fourth switches when a forward enable signal is enabled, and differentially control turn-on degrees of the first and second switches when a reverse enable signal is enabled.

Abstract: A memory includes a bit line, first to Nth cell groups (N?2), each with multiple memory cells connected to the bit line, and first to Nth current supply circuits supplying currents to the bit line. The first current supply circuit's current is determined by sensing the bit line current when input voltages are supplied to the first cell group. A kth current supply circuit's current (2?k?N) is determined by sensing the bit line current when input voltages are supplied to the first to kth cell groups, with the first to k?1th current supply circuits activated.

Abstract: A semiconductor device may include a cell bank in which a plurality of normal data storage regions and a plurality of ECC data storage regions corresponding to different numbers of bit lines are disposed on layers that are stacked, in a three-dimensional matrix form and a peripheral layer electrically connected to the cell bank and disposed under the layers of the cell bank, wherein the peripheral layer includes internal circuits configured to control the cell bank, the internal circuits comprising a plurality of test circuits configured to identify whether all data output from the plurality of normal data storage regions and the plurality of ECC data storage regions are identical with each other.

Abstract: A memory device includes a memory cell array and a regulator. The memory cell array includes a plurality of memory cells arranged in areas in which word lines and bit lines intersect with source lines, the word lines and the bit lines extending in a first direction and the source lines extending in the second direction. Memory cells along the first direction, among the plurality of memory cells, are electrically coupled to a same word line and a same bit line, memory cells along the second direction, among the plurality of memory cells, are electrically coupled to a same source line, and the bit lines are shunted at one or more shunt nodes. The regulator applies a bit line voltage to a common node at which the bit lines are electrically coupled in common.

Abstract: A memory may include a plurality of word lines formed of N layers, M word lines being arranged in each layer, among the plurality of word lines, where each of N and M is an integer of 2 or more; a plurality of bit line pillars; and a plurality of memory cells disposed at intersections between the plurality of word lines and the plurality of bit line pillars, respectively. Among the plurality of word lines, two or more word lines of the plurality of word lines may be grouped and driven together.

Abstract: A semiconductor memory apparatus is configured to perform a mismatch compensation operation of a bitline sense amplifier and enable a wordline electrically coupled with a bitline, after electrically isolating an input node of the bitline sense amplifier and the bitline. When the mismatch compensation operation of the bitline sense amplifier is completed, the semiconductor memory apparatus is configured to electrically couple the bitline and the input node of the bitline sense amplifier to develop a voltage level difference between the bitline and a bitline bar.

Abstract: A semiconductor device may include a bit line extending in a third direction, a plurality of active layers extending in a first direction and contacting the bit line, a plurality of word lines extending in a second direction and each disposed at an top surface or bottom surface of each of the plurality of active layers, a plurality of capacitors contacting the plurality of active layers, and a contact formed in at least one active layer disposed at the uppermost part of the bit line, among the plurality of active layers. The bit line and the contact may be electrically connected or separated by using, as a control line, a word line disposed in the top surface or bottom surface of the at least one active layer, among the plurality of word lines.

Abstract: Disclosed are a sigma-delta modulator that directly converts a current signal into digital data, an ADC utilizing the sigma-delta modulator, and a neural network computing system utilizing the ADC. The sigma-delta modulator includes: a delta circuit to generate a differential current between an analog current signal output from a resistive memory and a first current included in the analog current signal, the first current having an amount of current determined by a digital modulation signal; an integration circuit to generate an integration current by integrating the differential current; and a quantization circuit to generate the digital modulation signal corresponding to the integration current. The sigma-delta modulator can minimize the generation of noise by using no capacitor that performs a function by a switch, and can increase a signal processing speed for conversion by allowing the signal processing speed to be determined by a signal processing speed of one element.

Abstract: A nonvolatile memory apparatus may include a memory cell, a bit line control circuit, and a word line control circuit. The memory cell may be coupled between a global bit line and a global word line. During a read operation, the bit line control circuit may provide a first high voltage to the global bit line and provide a second high voltage to the global bit line when snapback of the memory cell occurs. During the read operation, the word line control circuit may provide a second read supply voltage to the global word line and provide an anneal supply voltage to the global word line when snapback of the memory cell occurs.

Abstract: A voltage generating circuit includes a voltage supplying circuit and a current biasing circuit. The voltage supplying circuit is configured to supply a first power voltage to an output node based on a first enable signal. The current biasing circuit is configured to control a bias current to flow from the output node based on a second enable signal. The second enable signal is enabled after the first enable signal is enabled.

Abstract: A nonvolatile memory apparatus performs a plurality of read operations by using a plurality of read voltages. A first read operation is performed by applying a first read voltage to a memory cell. A second read operation is selectively performed based on whether a snap-back of the memory cell occurs during the first read operation. The second read operation is performed by applying a second read voltage having a higher voltage level than the first read voltage to the memory cell.

Abstract: A voltage generating circuit includes a voltage supplying circuit and a current biasing circuit. The voltage supplying circuit is configured to supply a first power voltage to an output node based on a first enable signal. The current biasing circuit is configured to control a bias current to flow from the output node based on a second enable signal. The second enable signal is enabled after the first enable signal is enabled.

Abstract: A nonvolatile memory apparatus may include a memory cell, a bit line control circuit, and a word line control circuit. The memory cell may be coupled between a global bit line and a global word line. During a read operation, the bit line control circuit may provide a first high voltage to the global bit line and provide a second high voltage to the global bit line when snapback of the memory cell occurs. During the read operation, the word line control circuit may provide a second read supply voltage to the global word line and provide an anneal supply voltage to the global word line when snapback of the memory cell occurs.

Abstract: A voltage generating circuit includes a voltage supplying circuit and a current biasing circuit. The voltage supplying circuit is configured to supply a first power voltage to an output node based on a first enable signal. The current biasing circuit is configured to control a bias current to flow from the output node based on a second enable signal. The second enable signal is enabled after the first enable signal is enabled.

Abstract: A nonvolatile memory apparatus may include a memory cell, a bit line control circuit, and a word line control circuit. The memory cell may be coupled between a global bit line and a global word line. During a read operation, the bit line control circuit may provide a first high voltage to the global bit line and provide a second high voltage to the global bit line when snapback of the memory cell occurs. During the read operation, the word line control circuit may provide a second read supply voltage to the global word line and provide an anneal supply voltage to the global word line when snapback of the memory cell occurs.

Abstract: A voltage generating circuit includes a voltage supplying circuit and a current biasing circuit. The voltage supplying circuit is configured to supply a first power voltage to an output node based on a first enable signal. The current biasing circuit is configured to control a bias current to flow from the output node based on a second enable signal. The second enable signal is enabled after the first enable signal is enabled.

Abstract: A nonvolatile memory apparatus performs a plurality of read operations by using a plurality of read voltages. A first read operation is performed by applying a first read voltage to a memory cell. A second read operation is selectively performed based on whether a snap-back of the memory cell occurs during the first read operation. The second read operation is performed by applying a second read voltage having a higher voltage level than the first read voltage to the memory cell.

Abstract: A nonvolatile memory apparatus performs a plurality of read operations by using a plurality of read voltages. A first read operation is performed by applying a first read voltage to a memory cell. A second read operation is selectively performed based on whether a snap-back of the memory cell occurs during the first read operation. The second read operation is performed by applying a second read voltage having a higher voltage level than the first read voltage to the memory cell.

Abstract: A nonvolatile memory apparatus may include a memory cell, a bit line control circuit, and a word line control circuit. The memory cell may be coupled between a global bit line and a global word line. During a read operation, the bit line control circuit may provide a first high voltage to the global bit line and provide a second high voltage to the global bit line when snapback of the memory cell occurs. During the read operation, the word line control circuit may provide a second read supply voltage to the global word line and provide an anneal supply voltage to the global word line when snapback of the memory cell occurs.

Abstract: A nonvolatile memory apparatus performs a plurality of read operations by using a plurality of read voltages. A first read operation is performed by applying a first read voltage to a memory cell. A second read operation is selectively performed based on whether a snap-back of the memory cell occurs during the first read operation. The second read operation is performed by applying a second read voltage having a higher voltage level than the first read voltage to the memory cell.