Abstract: An electronic device includes a memory and a processor. The memory stores information related to an artificial intelligence model that performs arithmetic operations through neural network layers. The processor pre-processes raw data and obtains output data by inputting the pre-processed raw data to the artificial intelligence model. First data used for pre-processing the raw data and second data used in a portion of the neural network layers are stored in a secure area of the memory, and third data used in remaining layers of the neural network layers other than the portion is stored in a non-secure area of the memory.

Abstract: An System on Chip (SoC) including a secure element is provided. A method of the SoC comprises generating a random number when power is turned on, generating a seed table according to the random number on the basis of a seed table operation policy, masking a first data with a first data seed value corresponding to a target address in the seed table, encrypting the masked first data with a first type first encryption key in the seed table and writing the first encrypted first data to the target address of an external memory, wherein one of the data seed value or the first type first encryption key changes dynamically.

Abstract: An improved EMS (Energy Management System) of ESS (Energy Storage System)—connected photovoltaic power system is provided, where the economic efficiency of the microgrid power transaction is maximized by minimizing the amount paid to the power system as a result of optimal operation as to the energy supply and demand in the process of transacting power surplus/shortage with the power system, the responsiveness to passive resource energy forecasting of supply and demand is improved by resolving the uncertainty of solar power generation forecasting and load forecasting, the deterioration of the available storage capacity of ESS is minimized, and contribution to solving the nation's power supply shortage is made by the operation based on the detailed identification of energy storage status of ESS.

Abstract: A system on chip includes a host controller and a secure controller for securing communication between the system on chip and external devices accessing a memory controlled by a memory and an encryption/decryption module for encrypting and decrypting the data.

Abstract: A system on chip includes a host controller and a secure controller for securing communication between the system on chip and external devices accessing a memory controlled by a memory and an encryption/decryption module for encrypting and decrypting the data.

Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.

Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.

Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.

Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.

Abstract: An apparatus, method, chipset, and non-transitory computer-readable storage medium for controlling power are provided. The apparatus includes a receiver configured to receive a data frame and first information related to a next data frame of the data frame; and a controller configured to determine an operation mode as an active mode or a sleep mode based on destination address information of the next data frame and duration information indicating a time during which transmission of the next data frame occurs, wherein the destination address information and the duration information are included in the first information.

Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.

Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.

Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.

Abstract: A data processing system includes a master device and a slave device. The master device includes a first single pad, a first control circuit, a first frame generator configured, and a first processing circuit. The slave device includes a second single pad, a second control circuit, a second frame generator, and a second processing circuit. A clock source is configured to provide a clock signal to the master device and the slave device. The master device communicates with the slave device through a single wire, the single wire being connected between the first single pad and the second single pad, wherein the single wire is bidirectional. A first frame is transmitted from the master device to the slave device, and a second frame is transmitted from the slave device to the master device.

Abstract: A master device communicates with a slave device through an asynchronous serial communications link. The master device includes a single pad configured to communicate a command frame including an address and a data frame including data with the slave device via a single wire; and a processing circuit configured to generate an oversampling clock signal from a clock signal, to perform a synchronization process for selecting one of a plurality of clock phases of the oversampling clock signal, and to perform a sampling process for sampling an each bit value included in the data frame transmitted from the slave device using a clock phase at the same position as the clock phase selected during the synchronization process.

Abstract: A master device communicates with a slave device through an asynchronous serial communications link. The master device includes a single pad configured to communicate a command frame including an address and a data frame including data with the slave device via a single wire; and a processing circuit configured to generate an oversampling clock signal from a clock signal, to perform a synchronization process for selecting one of a plurality of clock phases of the oversampling clock signal, and to perform a sampling process for sampling an each bit value included in the data frame transmitted from the slave device using a clock phase at the same position as the clock phase selected during the synchronization process.

Abstract: A device and method for selectively using an internal memory and an external memory when processing Hybrid Automatic Repeat reQuest (HARQ) data are provided. The device includes a combiner configured to receive a first HARQ burst; an internal memory positioned within the device; and a memory selector configured to compare a size of the first HARQ burst with a predetermined threshold, to select one of the internal memory and an external memory positioned outside the device according to a comparison result, and to store the first HARQ burst in a selected memory. At least one among a size of the internal memory and the threshold is determined based on a characteristic of a first service type that has been predetermined.

Abstract: Methods and systems are provided for monitoring cyber activity in a system having multiple networks. A method includes: receiving an evidence stream generated by a plurality of monitoring systems associated with a plurality of hardware and software components that communicate over the multiple networks; processing the evidence stream using at least one reference model to identify at least one cyber issue, where the cyber issue relates to at least one of security, safety, and resources; and generating at least one of actuator data and user interface data based on the identified cyber issue.

Abstract: A master device communicates with a slave device through an asynchronous serial communications link. The master device includes a single pad configured to communicate a command frame including an address and a data frame including data with the slave device via a single wire; and a processing circuit configured to generate an oversampling clock signal from a clock signal, to perform a synchronization process for selecting one of a plurality of clock phases of the oversampling clock signal, and to perform a sampling process for sampling an each bit value included in the data frame transmitted from the slave device using a clock phase at the same position as the clock phase selected during the synchronization process.

Abstract: Methods, devices, and systems for encrypting a communication from a device are described herein. One device includes a memory, and a processor configured to execute executable instructions stored in the memory to generate a subset-sum problem and a Goldreich-Levin hash function and encrypt a communication from the device using the subset-sum problem and the Goldreich-Levin hash function.