Abstract: To prevent positional deviation in a folded back portion of a deployment restriction sheet reliably, an air bag device includes an air bag 1, an inflator 7 for deploying the air bag 1 by supplying the air bag with a generated gas, an air bag case 3 used to attach the inflator 7 and store the air bag 1, a retainer 6 for fixing an opening portion peripheral edge of the air bag 1 to the air bag case 3, and a deployment restriction sheet 11 that covers the air bag 1 from a vehicle body rear side to a vehicle body front side when the air bag 1 is stored. In the deployment restriction sheet 11, a folded back portion 11c is subjected to tacking 11d so as to separate upon application of a predetermined load A, and a rupturable portion 11e that ruptures upon application of a predetermined load B, which is larger than the load A, is provided on a first end 11a side positioned on the vehicle body front side. The first end 11a is attached to an air bag main body. A second end 11b is installed on the air bag main body.

Abstract: To prevent positional deviation in a folded back portion of a deployment restriction sheet reliably, an air bag device includes an air bag 1, an inflator 7 for deploying the air bag 1 by supplying the air bag with a generated gas, an air bag case 3 used to attach the inflator 7 and store the air bag 1, a retainer 6 for fixing an opening portion peripheral edge of the air bag 1 to the air bag case 3, and a deployment restriction sheet 11 that covers the air bag 1 from a vehicle body rear side to a vehicle body front side when the air bag 1 is stored. In the deployment restriction sheet 11, a folded back portion 11c is subjected to tacking 11d so as to separate upon application of a predetermined load A, and a rupturable portion 11e that ruptures upon application of a predetermined load B, which is larger than the load A, is provided on a first end 11a side positioned on the vehicle body front side. The first end 11a is attached to an air bag main body. A second end 11b is installed on the air bag main body.

Abstract: A semiconductor device includes a comparator which includes two input terminals and compares the voltage values between the power supply voltage which is inputted to one side input terminal and the reference voltage which is inputted to the other side input terminal. A resistor element connects two signal lines that are connected to the input terminals of the comparator One end of a capacitance element is connected to a power supply terminal for applying a power supply and the other end is connected to one input terminal of the comparator.

Abstract: A semiconductor device of the present invention includes a comparator (1) which includes two input terminals (N1), (N2), and compares the voltage values between the power supply voltage which is inputted to one side input terminal and the reference voltage which is inputted to the other side input terminal, a resister element (2) which connects the signal line (L1) which is connected the input terminal (N1) of the comparator (1) and the signal line (L2) which is the input terminal (N2) of the comparator (1), and a capacitance element (3) one end of which is connected to a power supply terminal for applying a power supply and the other end of which is connected to one input terminal of the comparator (2). Thereby, a step variation of a power supply voltage can be detected without depending on the power supply voltage before the voltage variation.

Abstract: The object of the invention is the provision of a semiconductor memory having processor and memory integrally mounted on one chip. To attain the object, crossbar wirings are laid on the memory cell area and crossbar switches are disposed in the sense amplifier area or word driver area. Accordingly, memory sharing is made possible without increasing the chip area and it is also made possible to take out a large number of data continuously. Hence, a memory-embedded system with a high bandwidth can be provided.

Abstract: The object of the invention is the provision of a semiconductor memory having processor and memory integrally mounted on one chip. To attain the object, crossbar wirings are laid on the memory cell area and crossbar switches are disposed in the sense amplifier area or word driver area. Accordingly, memory sharing is made possible without increasing the chip area and it is also made possible to take out a large number of data continuously. Hence, a memory-embedded system with a high bandwidth can be provided.

Abstract: The operating speed and stability of a semiconductor memory device of the type performing reading and writing at regular intervals are improved. A read/write pulse width controller varies the pulse width of a read/write pulse width control signal in such a manner that the width during reading is shorter than that during writing. A column decoder outputs a column-select signal having a pulse width equal to that of the read/write pulse width control signal. And a column-select gate connects an associated pair of bit lines to a pair of data lines while the column-select signal is high. During reading, a sufficiently long time can be allotted for equalizing potentials on the data lines. On the other hand, during writing, plenty of time can be allowed for connecting a pair of data lines to the pair of bit line. As a result, reading and writing can be performed stably enough at a sufficiently high speed.