Patents by Inventor Jun Hwe CHA

Jun Hwe CHA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260185959
    Abstract: A semiconductor device includes an integrated circuit structure disposed over a substrate and a hydrogen sensing structure disposed over the substrate to be laterally spaced apart from the integrated circuit structure. The integrated circuit structure includes an oxide semiconductor layer. The hydrogen sensing structure includes a hydrogen ion sensing layer containing a resistance change material, and a first sensing electrode layer and a second sensing electrode layer disposed at opposite ends of the hydrogen ion sensing layer. A bottom surface and a top surface of the hydrogen ion sensing layer are arranged to have same levels as a bottom surface and a top surface of the oxide semiconductor layer based on the surface of the substrate, respectively.
    Type: Application
    Filed: May 15, 2025
    Publication date: July 2, 2026
    Inventors: Jun Hwe CHA, Dong Jin KO, Se Hyun KIM, Wha Young KIM, Gyeong Cheol PARK
  • Patent number: 12671913
    Abstract: A semiconductor device may include a color filter array, an optical synapse array including a plurality of light passage paths transferring light incident through the color filter array with independently controlled transmissivities, and an optical-to-digital conversion circuit converting the transferred light through the plurality of light passage paths into digital data.
    Type: Grant
    Filed: December 7, 2023
    Date of Patent: June 30, 2026
    Assignee: SK hynix Inc.
    Inventors: Hyun Soo Kim, Jeong Hwan Song, Jun Hwe Cha, Youn Jae Song
  • Publication number: 20260143698
    Abstract: The semiconductor device includes a first channel structure; a first air layer surrounding a side surface of the first channel structure; a first bitline contacting the side surface of the first channel structure; a first wordline contacting a lower portion of the first channel structure; a storage node having one end contacting an upper portion of the first channel structure; a second channel structure contacting an upper portion of the storage node; a second air layer surrounding a side surface of the second channel structure; a second bitline contacting the side surface of the second channel structure; and a second wordline contacting an upper portion of the second channel structure. The first bitline extends in a direction perpendicular to a direction in which the first channel structure extends. The second wordline extends in a direction perpendicular to a direction in which the second channel structure extends.
    Type: Application
    Filed: September 23, 2025
    Publication date: May 21, 2026
    Inventors: Wha Young KIM, Gyeong Cheol PARK, Jung Wook WOO, Byoung Seok LEE, Jun Hwe CHA
  • Publication number: 20260143667
    Abstract: A semiconductor device includes a first bitline extending in a first direction, a first wordline extending in a second direction crossing the first direction, a first active region contacting the first bitline, a back-gate extending parallel to the first wordline, and a storage transistor contacting the first active region. The first active region is disposed between the first wordline and the back-gate, and includes a vertical portion extending in a third direction crossing the first and second directions and a horizontal portion that contacts one end of the vertical portion and the first bitline.
    Type: Application
    Filed: October 15, 2025
    Publication date: May 21, 2026
    Inventors: Jun Hwe CHA, Wha Young KIM
  • Patent number: 12598855
    Abstract: A memristor device, a fabricating method thereof, a synaptic device including the memristor device, and a neuromorphic device including the synaptic device are provided. The memristor device includes a first electrode, a second electrode spaced apart from the first electrode, a resistance change layer disposed between the first electrode and the second electrode and including a polymer, and an insertion layer disposed between the first electrode and the resistance change layer and including an oxide. An electrochemical metallization mechanism (ECM) filament is formed in the resistance change layer, and a valence change mechanism (VCM) filament is formed in the insertion layer. The memristor device has a synaptic characteristic according to a change in resistance of the resistance change layer. The insertion layer includes an Al2O3 layer. The insertion layer includes an Al2O3 layer formed by an atomic layer deposition (ALD) process using a temperature of about 200° C. or higher.
    Type: Grant
    Filed: March 22, 2023
    Date of Patent: April 7, 2026
    Assignees: SK hynix Inc., Korea Advanced Institute of Science and Technology
    Inventors: Sang Su Park, Sung Yool Choi, Jun Hwe Cha, Jung Yeop Oh
  • Publication number: 20260090029
    Abstract: A semiconductor device includes: a substrate; two heating patterns arranged to be spaced apart from each other over the substrate; two metal oxide patterns respectively positioned over the two heating patterns; two second oxide semiconductor patterns comprising source/drain regions and respectively positioned over the two metal oxide patterns; a first oxide semiconductor pattern forming a channel region positioned between the two second oxide semiconductor patterns; a gate electrode positioned over or below the first oxide semiconductor pattern; and a gate dielectric layer interposed between the gate electrode and the first oxide semiconductor pattern, wherein an oxygen density of the two second oxide semiconductor patterns is smaller than an oxygen density of the first oxide semiconductor pattern.
    Type: Application
    Filed: December 3, 2025
    Publication date: March 26, 2026
    Inventor: Jun Hwe CHA
  • Publication number: 20260056249
    Abstract: A semiconductor device including a hydrogen test pattern for testing the influence of hydrogen on an insulation layer is disclosed. The semiconductor device includes a target insulation layer shared by a transistor pattern disposed in a first region and a test pattern disposed in a second region. The test pattern includes detection interconnect elements disposed within the target insulation layer, and outputs a test current corresponding to a test voltage provided through the detection interconnect elements.
    Type: Application
    Filed: August 14, 2025
    Publication date: February 26, 2026
    Inventors: Wha Young KIM, Dong Jin KO, Se Hyun KIM, Gyeong Cheol PARK, Jun Hwe CHA
  • Patent number: 12532512
    Abstract: A semiconductor device includes: a substrate; two heating patterns arranged to be spaced apart from each other over the substrate; two metal oxide patterns respectively positioned over the two heating patterns; two second oxide semiconductor patterns comprising source/drain regions and respectively positioned over the two metal oxide patterns; a first oxide semiconductor pattern forming a channel region positioned between the two second oxide semiconductor patterns; a gate electrode positioned over or below the first oxide semiconductor pattern; and a gate dielectric layer interposed between the gate electrode and the first oxide semiconductor pattern, wherein an oxygen density of the two second oxide semiconductor patterns is smaller than an oxygen density of the first oxide semiconductor pattern.
    Type: Grant
    Filed: August 2, 2023
    Date of Patent: January 20, 2026
    Assignee: SK hynix Inc.
    Inventor: Jun Hwe Cha
  • Publication number: 20250344452
    Abstract: A semiconductor device includes a crystalline first oxide semiconductor pattern having at least one etched surface; and a crystalline second oxide semiconductor layer disposed on the etched surface of the first oxide semiconductor pattern. A method for fabricating a semiconductor device includes forming a crystalline first oxide semiconductor layer over a substrate; forming a first oxide semiconductor pattern having an etched side surface by selectively etching the first oxide semiconductor layer; and forming a crystalline second oxide semiconductor layer on the side surface of the first oxide semiconductor pattern.
    Type: Application
    Filed: October 29, 2024
    Publication date: November 6, 2025
    Inventors: Jun Hwe CHA, Wha Young KIM
  • Publication number: 20250063264
    Abstract: A semiconductor device may include a color filter array, an optical synapse array including a plurality of light passage paths transferring light incident through the color filter array with independently controlled transmissivities, and an optical-to-digital conversion circuit converting the transferred light through the plurality of light passage paths into digital data.
    Type: Application
    Filed: December 7, 2023
    Publication date: February 20, 2025
    Inventors: Hyun Soo KIM, Jeong Hwan SONG, Jun Hwe CHA, Youn Jae SONG
  • Publication number: 20240274722
    Abstract: A semiconductor device includes: a substrate; two heating patterns arranged to be spaced apart from each other over the substrate; two metal oxide patterns respectively positioned over the two heating patterns; two second oxide semiconductor patterns comprising source/drain regions and respectively positioned over the two metal oxide patterns; a first oxide semiconductor pattern forming a channel region positioned between the two second oxide semiconductor patterns; a gate electrode positioned over or below the first oxide semiconductor pattern; and a gate dielectric layer interposed between the gate electrode and the first oxide semiconductor pattern, wherein an oxygen density of the two second oxide semiconductor patterns is smaller than an oxygen density of the first oxide semiconductor pattern.
    Type: Application
    Filed: August 2, 2023
    Publication date: August 15, 2024
    Inventor: Jun Hwe CHA
  • Publication number: 20230309327
    Abstract: A memristor device, a fabricating method thereof, a synaptic device including the memristor device, and a neuromorphic device including the synaptic device are provided. The memristor device includes a first electrode, a second electrode spaced apart from the first electrode, a resistance change layer disposed between the first electrode and the second electrode and including a polymer, and an insertion layer disposed between the first electrode and the resistance change layer and including an oxide. An electrochemical metallization mechanism (ECM) filament is formed in the resistance change layer, and a valence change mechanism (VCM) filament is formed in the insertion layer. The memristor device has a synaptic characteristic according to a change in resistance of the resistance change layer. The insertion layer includes an Al2O3 layer. The insertion layer includes an Al2O3 layer formed by an atomic layer deposition (ALD) process using a temperature of about 200° C. or higher.
    Type: Application
    Filed: March 22, 2023
    Publication date: September 28, 2023
    Inventors: Sang Su PARK, Sung Yool Choi, Jun Hwe Cha, Jung Yeop Oh
  • Patent number: 11552267
    Abstract: The present disclosure provides a soft memristor for soft neuromorphic system including a substrate, a first electrode layer formed on the substrate, a metal diffusion barrier layer formed on the first electrode layer, a resistive switching material layer formed on the metal diffusion barrier layer, and a second electrode layer formed on the resistive switching material layer.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: January 10, 2023
    Assignee: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Sung-Yool Choi, Byung Chul Jang, Jun Hwe Cha
  • Publication number: 20210143349
    Abstract: The present disclosure provides a soft memristor for soft neuromorphic system including a substrate, a first electrode layer formed on the substrate, a metal diffusion barrier layer formed on the first electrode layer, a resistive switching material layer formed on the metal diffusion barrier layer, and a second electrode layer formed on the resistive switching material layer.
    Type: Application
    Filed: July 29, 2020
    Publication date: May 13, 2021
    Inventors: Sung-Yool Choi, Byung Chul Jang, Jun Hwe Cha
  • Patent number: 10613068
    Abstract: Disclosed are polymer nanofiber sensors for detecting gas, which generates visible color change although a specific gas having a concentration of less than 1 ppm is exposed to the sensor in a short time, in which it is impossible to detect the gas using existing colorimetric sensors, through securing high surface area and porosity, and a method of the same.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: April 7, 2020
    Assignee: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Il-Doo Kim, Jun Hwe Cha, Won-Tae Koo
  • Publication number: 20170261479
    Abstract: Disclosed are polymer nanofiber sensors for detecting gas, which generates visible color change although a specific gas having a concentration of less than 1 ppm is exposed to the sensor in a short time, in which it is impossible to detect the gas using existing colorimetric sensors, through securing high surface area and porosity, and a method of the same.
    Type: Application
    Filed: March 9, 2017
    Publication date: September 14, 2017
    Applicant: Korea Advanced Institute of Science and Technology
    Inventors: Il-Doo KIM, Jun Hwe CHA, Won-Tae KOO